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| 型号： | MAX6951CEE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 11/19页 |
| 文件大小： | 0K |
| 描述： | IC DRVR DSPL LED SRL 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | 3 线串口 |
| 数字或字符： | 8 位数字 |
| 电流 - 电源： | 10mA |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-LSSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 10. Global Clear Digit Data (R Data Bit D5) Format
MODE
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Digit data for both
planes P0 and P1 are
0x04
X
X
0
T
E
B
0
S
unaffected
Digit data for both
planes P0 and P1 are
cleared on the rising
0x04
X
X
1
T
E
B
0
S
edge of CS
Table 11. Display-Test Register Format
MODE
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
Normal operation
Display test
0x07
0x07
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Table 12. Scan-Limit Register Format
SCAN LIMIT
ADDRESS
CODE (HEX)
D7
D6
D5
REGISTER DATA
D4 D3
D2
D1
D0
HEX
CODE
Display digit 0 only
Display digits 0 and 1
Display digits 0 and 1 2
Display digits 0 and 1 2 3
Display digits 0 and 1 2 3 4
Display digits 0 and 1 2 3 4 5
Display digits 0 and 1 2 3 4 5 6
Display digits 0 and 1 2 3 4 5 6 7
0x03
0x03
0x03
0x03
0x03
0x03
0x03
0x03
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0xX0
0xX1
0xX2
0xX3
0xX4
0xX5
0xX6
0xX7
If the blink function is disabled through the Blink Enable
Bit E (Table 8) in the configuration register, then the digit
register data in plane P0 is used to multiplex the display.
The digit register data in P1 is not used (Table 17).
If the blink function is enabled, then the digit register
data in both plane P0 and plane P1 are alternately used
to multiplex the display. Blinking is achieved by multi-
plexing the LED display using data plane P0 and plane
P1 on alternate phases of the blink clock (Table 18).
Display Blink Mode
The display blinking facility, when enabled, makes the
driver flip automatically between displaying the digit
register data in planes P0 and plane P1. If the digit reg-
ister data for any individual segment is different in the
two planes, then that segment appears to blink or flash
on and off. Once blinking has been configured, it con-
tinues automatically without further intervention.
Blink Speed
The blink speed is determined by frequency of the mul-
tiplex clock, OSC, and by the setting of the Blink Rate
Selection Bit B (Table 7) in the configuration register.
The Blink Rate Selection Bit B sets either fast or slow
blink speed for the whole display.
Multiplex Clock and OSC Oscillator
The OSC input pin is used to set both the display scan
rate and the blink timing for the display driver. OSC
must either be fitted with an external capacitor C SET to
GND to set the frequency of the MAX6950/MAX6951s’
internal RC oscillator, or be overdriven with an external
TTL/CMOS clock.
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