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参数资料
| 型号： | MAX6951CEE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | IC DRVR DSPL LED SRL 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | 3 线串口 |
| 数字或字符： | 8 位数字 |
| 电流 - 电源： | 10mA |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-LSSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 17. Digit Register Mapping with
Blink Globally Disabled
V+ = supply voltage
DUTY = duty cycle set by intensity register
SEGMENT’S
BIT SETTING
IN PLANE P1
X
X
SEGMENT’S
BIT SETTING
IN PLANE P0
0
1
SEGMENT
BEHAVIOR
Segment off during both
halves of each blink
period
Segment off during both
halves of each blink
period
N = number of segment driven (worst case is 8)
V LED = LED forward voltage
I SEG = segment current set by R SET
PD = power dissipation, in mW if currents are in mA
Dissipation example:
I SEG = 40mA, N = 8, Duty = 15/16, V LED = 2.4V at
40mA, V+ = 3.6V
P D = 3.6V (15mA) + (3.6V - 2.4V)(15 / 16 ? 40mA x 8)
= 0.414W
Table 18. Digit Register Mapping with
Blink Globally Enabled
Thus, for the 16-pin QSOP package (T JA = 1/0.00834 =
+120°C/W), the maximum allowed ambient temperature
SEGMENT’S
BIT SETTING
IN PLANE P1
0
0
1
1
SEGMENT’S
BIT SETTING
IN PLANE P0
0
1
0
1
SEGMENT
BEHAVIOR
Segment off
Segment on only during
the 1st half of each blink
period
Segment on only during
the 2nd half of each blink
period
Segment on
T A is given by:
T J (MAX) = T A + (P D ? T JA ) = +150°C = T A + (0.44 ?
+120°C/W)
So T A = +100°C. Thus, the device can be operated
safely at a maximum package temperature of +85°C.
Power Supplies
The MAX6950/MAX6951 operate from a single +2.7V to
+5.5V power supply. Bypass the power supply to
ground with a 0.1μF capacitor as close to the pin as
possible. Add a 22μF capacitor if the MAX6950/
MAX6951 are not close to the board’s input bulk decou-
pling capacitor.
be unable to regulate the current correctly. As the sup-
ply voltage drops further, the LED segment drive cur-
rent becomes effectively limited by the output drivers'
on-resistance, and the LED drive current drops. The
characteristics of each individual LED in a modern 7-
segment digit usually match well, so the result is that
the display intensity dims uniformly as supply voltage
drops out of regulation and beyond. The MAX6950/
MAX6951 operate down to 2V supply voltage (although
most displays are very dim at this voltage), providing
that the MAX6950/MAX6951 are powered up initially to
at least 2.7V to trigger the device's internal reset, and
also that the SPI interface is constrained to 5Mbps.
Computing Power Dissipation
The upper limit for power dissipation (PD) for the
MAX6950/MAX6951 is determined from the following
equation:
P D = (V+ x I+) + (V+ - V LED ) (DUTY ? I SEG ? N)
Where:
Connect the underside exposed pad to GND.
Board Layout
When designing a board, use the following guidelines:
1. The R SET connection to pin 7 is a high-impedance
node, and sensitive to layout. Place R SET right next
to pins 7 and 8 and route R SET directly to these pins
with very short tracks.
2. Ensure that the track from the ground end of R SET
routes directly to pin 8, and that this track is not
used as part of any other ground connection.
Figure 5 shows a good layout. The decoupling capaci-
tors C1 (ceramic) and C2 (bulk, if required) are located
above the IC. The ground track to R SET is a separate
track from both the IC's power ground connection and
the ground plane.
16
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