参数资料
型号: MAX6951CEE+T
厂商: Maxim Integrated
文件页数: 7/19页
文件大小: 0K
描述: IC DRVR DSPL LED SRL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
显示器类型: LED
配置: 7 段显示
接口: 3 线串口
数字或字符: 8 位数字
电流 - 电源: 10mA
电源电压: 2.7 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-LSSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP 裸露焊盘
包装: 带卷 (TR)
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
CS
t CSW
CLK
t CSS
t DS
t DH
t CL
t CH
t CP
t CSH
DIN
D15
D14
D1
D0
Figure 1. Timing Diagram
CS
CLK
DIN
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. Transmission of 16 Bits to the MAX6950/MAX6951
CS
CLK
DIN
BIT1
BIT2
N-15
N-14
N-13
N-12
N-11
N-10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
Figure 3 . Transmission of More than 16 Bits to the MAX6950/MAX6951
control registers remains unaltered. Shutdown can be
used to save power. For minimum supply current in
shutdown mode, logic inputs should be at ground or
V+ (CMOS-logic levels). The display driver can be pro-
grammed while in shutdown mode, and shutdown
mode can be overridden by the display test function.
Table 7 lists the blink rate selection format.
If blink is globally enabled by setting the E bit of the
configuration register (Table 8), then the digit data in
both planes P0 and P1 are used to control the display
(Table 9).
When the global blink timing synchronization bit is set,
the multiplex and blink timing counter is cleared on the
rising edge of CS . By setting the T bit in multiple
MAX6950/MAX6951s at the same time (or in quick suc-
cession), the blink timing can be synchronized across
all the devices.
When the global digit data clear (R data bit D5) is set,
the digit data for both planes P0 and P1 for ALL digits
is cleared on the rising edge of CS . Digits with decode
enabled display the zero. Digits without decode
enabled show all segments unlit.
_______________________________________________________________________________________
7
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