参数资料
型号: MAX7033EUI+T
厂商: Maxim Integrated
文件页数: 14/16页
文件大小: 0K
描述: IC RX 315MHZ/433MHZ ASK 28TSSOP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 315MHz,433MHz
灵敏度: -114dBm
数据传输率 - 最大: 33 kbps
调制或协议: ASK
应用: 汽车 RKE,遥控,无线传感器
电流 - 接收: 5.2mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 105°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ /10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace con-
necting a 100nH inductor adds an extra 10nH of induc-
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to
ground on all GND pins, and place decoupling capaci-
tors close to all power-supply pins.
Control Interface Considerations
When operating the MAX7033 with a +4.5V to +5.5V
supply voltage, the SHDN and AC pins can be driven
by a microcontroller with either 3V or 5V interface logic
levels. When operating the MAX7033 with a +3.0V to
+3.6V supply, only 3V logic from the microcontroller is
allowed.
tance or 10%.
Typical Application Circuit
V DD3
V DD
IF V DD IS
THEN V DD3 IS
(SEE TABLE)
3.0V TO 3.6V CONNECTED TO V DD
CREATED BY LDO,
4.5V TO 5.5V AVAILABLE AT AVDD
X1
RF INPUT
(PIN 2)
C1
C11
L1
C13
1
2
3
XTAL1
AVDD
LNAIN
XTAL2
SHDN
PDOUT
28
27
26
C12
TO/FROM μ P
POWER-DOWN
DATA OUT
V DD3
L2
C14
4
5
6
LNASRC
AGND
LNAOUT
MAX7033
DATAOUT
V DD5
DSP
25
24
23
C15
R2
R3
C9
L3
C2
C3
C4
7
8
9
10
AVDD
MIXIN1
MIXIN2
AGND
DFFB
OPP
DSN
DFO
22
21
20
19
C7
11
IRSEL
IFIN2
18
12
13
MIXOUT
DGND
IFIN1
XTALSEL
17
16
R1
**
14
DVDD
AC
15
C5
C6
C8
FROM μ P
Y1
*
COMPONENT VALUES
IN TABLE 1
C10
**SEE THE MIXER SECTION.
IF FILTER
IN OUT
GND
*SEE PHASE-LOCKED LOOP SECTION.
14
______________________________________________________________________________________
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