参数资料
型号: MAX7033EUI+T
厂商: Maxim Integrated
文件页数: 9/16页
文件大小: 0K
描述: IC RX 315MHZ/433MHZ ASK 28TSSOP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
频率: 315MHz,433MHz
灵敏度: -114dBm
数据传输率 - 最大: 33 kbps
调制或协议: ASK
应用: 汽车 RKE,遥控,无线传感器
电流 - 接收: 5.2mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 105°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 带卷 (TR)
315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Pin Description (continued)
TSSOP
28
PIN
THIN QFN
28
1, 13,
21, 25
NAME
XTAL2
N.C
EP
FUNCTION
Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal
Oscillator section.)
No Connection
Exposed Pad (TQFN Only). Connect EP to GND.
Functional Diagram
LNASRC
4
AC
15
LNAOUT
6
MIXIN1 MIXIN2
8 9
IRSEL
11
MIXOUT
12
IFIN1
17
IFIN2
18
28-PIN TSSOP
PACKAGE
LNAIN
3
LNA
AUTOMATIC
GAIN
CONTROL
Q
0?
IMAGE
REJECTION
IF LIMITING
AMPS
AVDD
V DD5
AVDD
DVDD
DGND
2
24
7
14
13
3.2V REG
DIVIDE
BY 64
PHASE
DETECTOR
VCO
LOOP
FILTER
I
90?
MAX7033
RSSI
R DF2
100k Ω
DATA
FILTER
R DF1
100k Ω
DATA
AGND
5, 10
÷ 1
÷ 2
CRYSTAL
DRIVER
POWER-
DOWN
SLICER
16
1
28
27
25
20
23
19
26
21
22
XTALSEL
XTAL1 XTAL2
SHDN
DATAOUT
DSN DSP DFO
PDOUT
OPP
DFFB
Detailed Description
The MAX7033 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps Manchester (66kbps
NRZ) can be achieved.
The MAX7033 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
Voltage Regulator
For operation with a single +3.0V to +3.6V supply voltage,
connect AVDD, DVDD, and V DD5 to the supply voltage.
For operation with a single +4.5V to +5.5V supply voltage,
connect V DD5 to the supply voltage. An on-chip voltage
regulator drives one of the AVDD pins to approximately
+3.2V. For proper operation, DVDD and both the AVDD
pins must be connected together. Bypass V DD5 , DVDD,
and the pin 7 AVDD pin to AGND with 0.01μF capacitors,
and the pin 2 AVDD pin to AGND with a 0.1μF capacitor,
all placed as close as possible to the pins.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration, with a 3.0dB noise figure and
an IIP3 of -12dBm. The gain and noise figures are
dependent on both the antenna matching network at
the LNA input and the LC tank network between the
LNA output and the mixer inputs.
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