参数资料
型号: MAX7042ATJ+
厂商: Maxim Integrated
文件页数: 8/17页
文件大小: 0K
描述: IC RCVR RF LP FSK 32-TQFN-EP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
频率: 308MHz,315MHz,418MHz,433.92MHz
灵敏度: -110dBm
数据传输率 - 最大: 66 kbps
调制或协议: FSK
应用: 门禁控制,AMR,ISM,RKE,TPM
电流 - 接收: 7.2mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
电源电压: 2.4 ~ 3.6 V & 4.5 ~ 5.5 V
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
产品目录页面: 1424 (CN2011-ZH PDF)
308MHz/315MHz/418MHz/433.92MHz
Low-Power, FSK Superheterodyne Receiver
Pin Description
PIN
1, 2
3, 25, 32
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
31
EP
NAME
N.C.
N.C.
RSSI
XTAL2
XTAL1
AVDD
LNAIN
LNASRC
LNAOUT
MIXIN+
MIXIN-
MIXOUT
AGND
IFIN-
IFIN+
PDMIN
PDMAX
DS-
DS+
OP+
DF
DGND
DVDD
EN
FSEL1
FSEL2
HVIN
DATA
LNASEL
GND
FUNCTION
No Connection. Internally pulled down.
No Connection. Not internally connected.
Buffered Received-Signal-Strength-Indicator Output
Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference.
Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.
Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in +5V operation.
Bypass AVDD to GND with 0.1μF and 220pF capacitors placed as close to the pin as possible.
Low-Noise Amplifier Input. Must be AC-coupled.
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
Low-Noise Amplifier Output. Connect to V AVDD through a parallel LC tank filter. AC-couple to MIXIN+.
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
Inverting Mixer Input. Bypass to V AVDD or AGND with a capacitor.
330 ? Mixer Output. Connect to the input of the 10.7MHz IF filter.
Analog Ground
Inverting 330 ? IF Limiter Amplifier Input. Bypass to AGND with a capacitor.
Noninverting 330 ? IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for Demodulator Output
Maximum-Level Peak Detector for Demodulator Output
Inverting Data-Slicer Input
Noninverting Data-Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Digital Ground
Digital Power-Supply Voltage. Bypass to DGND with 0.01μF and 220pF capacitors placed as close to
the pin as possible.
Enable. Internally pulled down. Drive high for normal operation. Drive low or leave unconnected to put
the device into shutdown mode.
Frequency-Select Pin 1 (see Table 1). Internally pulled down. Connect to EN for logic-high operation.
Frequency-Select Pin 2 (see Table 1). Internally pulled down. Connect to EN for logic-high operation.
High-Voltage Supply Input. For +3V operation, connect HVIN to AVDD and DVDD. For +5V operation,
connect only HVIN to +5V. Bypass HVIN to AGND with 0.01μF and 220pF capacitors placed as close
to the pin as possible.
Receiver Data Output
LNA Bias Current Select Pin. Internally pulled down. Set LNASEL to logic-low for low LNA current and
set LNASEL to logic-high for high LNA current. Connect to EN for logic-high operation.
Exposed Pad. Connect to ground.
8
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