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| 型号： | MAX7369EUP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC MULTIPLEXER DUAL 4X1 20TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 多路复用器 |
| 电路： | 2 x 4:1 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 2.3 V ~ 5.5 V |
| 电流 - 电源： | 6µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
_______________________________________________________________________________________
5
Note 1: All parameters are production tested at TA = +25°C and guaranteed by design over the specified temperature range.
Note 2: Minimum value is not production tested. Guaranteed by design.
Note 3: Pass gate propagation delay is calculated from 20
Ω (typ) RON and the 15pF load capacitance. Not production tested.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL) in order to
bridge the undefined region of SCL’s falling edge.
Note 5: Cb = total capacitance of one bus line in pF.
Note 6: Guaranteed by design.
Note 7: Measurements taken with a 1k
Ω pullup resistor and 50pF load.
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fSCL = 100kHz
300
Fall Time of Both SDA and SCL
Signals
tf
fSCL = 400kHz (Note 5)
20 +
0.1Cb
300
ns
Capacitive Load for Each Bus Line
Cb
(Note 6)
400
pF
Pulse Width of Spikes Suppressed
tSP
50
ns
Data Valid Time from High to Low
tVD;DATL
(Note 7)
1
s
Data Valid Time from Low to High
tVD;DATH
(Note 7)
0.6
s
Data Valid Acknowledge
tVD;ACK
1s
INT (Figure 2)
INT_ to INT Active Valid Time
tIV
4s
INT_ to INT Inactive Delay Time
tIR
2s
Low-Level, Pulse-Width Rejection
or
INT_ Inputs
tW(REJ)L
1s
High-Level, Pulse-Width Rejection
or
INT_ Inputs
tW(REJ)H
0.5
s
RESET (Figure 3)
Pulse-Width Low Reset
tWL(RST)
4ns
Reset Time (SDA Clear)
tRST
500
ns
Recovery to Start
tREC;STA
0ns
SDA
SCL
tBUF
tSU;STO
tr
tSP
tHD;STA
tSU;STA
tf
tHIGH
tSU;DAT
tHD;DAT
tr
tLOW
tHD;STA
tf
S
Sr
P
Figure 1. 2-Wire Serial-Interface Timing Diagram
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