参数资料
型号: MAX7369EUP+T
厂商: Maxim Integrated Products
文件页数: 6/19页
文件大小: 0K
描述: IC MULTIPLEXER DUAL 4X1 20TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 多路复用器
电路: 2 x 4:1
电压电源: 单电源
电压 - 电源,单路/双路(±): 2.3 V ~ 5.5 V
电流 - 电源: 6µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
MAX7367/MAX7368/MAX7369
4-Channel I2C Switches/Multiplexer
14
______________________________________________________________________________________
RESET Input (MAX7367/MAX7368)
The MAX7367/MAX7368 feature an active-low
RESET
input. When
RESET is driven low for more than 4ns, the
MAX7367/MAX7368 reset the internal register and I2C
state machine to their default states, allowing a master
to recover from a bus fault condition.
Power-On Reset (POR)
When power is applied to VDD, internal POR circuitry
holds the MAX7367/MAX7368/MAX7369 in a reset state
until VDD has reached the VPOR threshold. At this point,
the reset condition is released, and the MAX7367/
MAX7368/MAX7369 register and I2C state machine are
initialized to their default states (all zeroes), causing all
the channels to be deselected.
Voltage Translation
The MAX7367/MAX7368/MAX7369 can be used as a volt-
age translator from the main bus to the extended buses.
The output voltage (VPASS) is limited by the supply volt-
age (VDD) (see the Typical Operation Characteristics).
For the MAX7367/MAX7368/MAX7369 to be used as a
voltage translator, the VPASS voltage should be lower
than or equal to the lowest bus voltage.
I2C Interface
The MAX7367/MAX7368/MAX7369 feature an I2C-com-
patible, 2-wire serial interface consisting of a bidirec-
tional serial-data line (SDA) and a serial-clock line
(SCL). The master (typically a microcontroller) initiates
data transfer on the bus and generates the SCL.
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 9).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 10).
Acknowledge Bit
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (NA).
Both the master and the MAX7367/MAX7368/MAX7369
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related
clock pulse (ninth pulse) and keep it low during the
high period of the clock pulse (Figure 11). In the case
of an unsuccessful data transfer, the receiver allows
SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
SDA
SCL
DATA STABLE
DATA VALID
CHANGE OF
DATA ALLOWED
Figure 9. Bit Transfer
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 10. Start and Stop Conditions
CLOCK PULSE FOR
ACKNOWLEDGMENT
NOT ACKNOWLEDGE
ACKNOWLEDGE
12
8
9
SDA
SCL
START
CONDITION
Figure 11. Acknowledge
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