参数资料
型号: MAX8554EEE+T
厂商: Maxim Integrated Products
文件页数: 21/24页
文件大小: 0K
描述: IC CNTRLR BUCK PWM 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
应用: 控制器,DDR,DDR2
输入电压: 4.5 V ~ 28 V
输出数: 1
输出电压: 0.6 V ~ 3.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
4.5V to 28V Input, Synchronous PWM Buck Controllers
for DDR Termination and Point-of-Load Applications
Setting Voltage Positioning
The droop resistor, R DRP (R4) in Figure 2, in series with
the output inductor before the output capacitor, sets the
droop voltage, V DRP . Choose R DRP such that the output
voltage at the maximum load current, including ripple, is
just above the lower limit of the output tolerance:
Choose the MOSFETs with rated R DS(ON) at V GS = 4.5V.
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to switching loss at nominal input voltage and
maximum output current (see below). For the low-side
MOSFET, make sure that it does not spuriously turn on
because of the dV/dt caused by the high-side MOSFET
R DRP <
V OUT( TYP) - V OUT(MIN) - V RIPPLE / 2
I OUT ( MAX )
turning on, as this would result in shoot-through current
degrading the efficiency. MOSFETs with a lower Q GD to
Q GS ratio have higher immunity to dV/dt.
R DRP introduces some power dissipation, which is
given by:
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
P D ( DRP ) = R DRP ( OUT ( MAX )
× I
) 2
worst-case input voltage (for low-side MOSFET, worst
case is at V IN(MAX) ; for high-side MOSFET, it could be
either at V IN(MIN) or V IN(MAX) ). The high-side MOSFET
P LSCC = ? 1 - OUT ? × ( I LOAD DS ( ON )
) 2 × R
R DRP should be chosen to handle this power dissipation.
Power MOSFET Selection
The MAX8553/MAX8554 drive external, logic-level, N-
channel MOSFETs as the circuit-switch elements. The
key selection parameters are:
On-resistance (R DS(ON) ): The lower, the better.
Maximum drain-to-source voltage (V DSS ): This
should be at least 20% higher than the input supply rail
at the high-side MOSFET’s drain.
Gate charges (Q G , Q GD , Q GS ): The lower, the better.
R1
VIN
and low-side MOSFET have different loss components
due to the circuit operation. The low-side MOSFET
operates as a zero voltage switch; therefore, major
losses are: the channel conduction loss (P LSCC ), the
body-diode conduction loss (P LSDC ), and the gate-
drive loss (P LSDR ):
? V ?
? V IN ?
Use R DS(ON) at T J(MAX):
P LSDC = 2 × I LOAD × V F × t DT × f S
where V F is the body-diode forward-voltage drop, t DT is
the dead time (~30ns), and f S is the switching frequency.
Because of the zero-voltage switch operation, low-side
Q3
POK
V+
REFIN
MAX8553
VL
BST
DH
MOSFET gate-drive loss occurs as a result of charging
and discharging the input capacitance (C ISS ). This loss
is distributed among the average DL gate driver ’s
pullup and pulldown resistance, R DL (~1.2 ? ), and the
internal gate resistance (R GATE ) of the MOSFET (~2 ? ).
The drive power dissipated is given by:
P LSDR ISS × ( V GS ) × f S ×
= C
SDN
2N7002
EN/HSD
REF
LX
DL
2
R GATE
R GATE + R DL
R6
10k ?
R2
ILIM
FSEL
PGND
VTT
The high-side MOSFET operates as a duty-cycle con-
trol switch and has the following major losses: the
channel conduction loss (P HSCC ), the VI overlapping
switching loss (P HSSW ), and the drive loss (P HSDR ).
GND
VTTR
The high-side MOSFET does not have body-diode con-
duction loss because the diode never conducts current.
Figure 6. A resistor-divider (R1 and R2) is used to lower the
switching frequency.
______________________________________________________________________________________
21
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