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参数资料
| 型号： | MAX8588ETM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/31页 |
| 文件大小： | 0K |
| 描述： | IC PMIC HI EFF LOW IQ 48-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
High-Efficiency, Low-I Q PMIC with
Dynamic Core for PDAs and Smartphones
Pin Description (continued)
PIN
35
36
37
38
39
40
41
42
43
44
45
46
47
48
EP
NAME
SRAD
RSO
MR
CC3
FB3
ON6
V6
IN6
PG1
LX1
PV1
ON1
SLP
DBI
EP
FUNCTION
Serial Address Bit. SRAD allows the serial address to be changed in case it conflicts with another serial
device. If SRAD = GND, A1 = 0. If SRAD = IN, A1 = 1.
Open-Drain Reset Output. Deasserts when V7 exceeds 2.55V (typ rising). Has 65ms delay before release.
RSO is expected to connect to nRESET on the CPU.
Manual Reset Input. A low input at MR causes the RSO output to go low and also resets the V3 output to its
default 1.3V setting. MR impacts no other functions.
REG 3 Compensation Node. Connect a series resistor and capacitor from CC3 to GND to compensate the
regulation loop. See the Compensation and Stability section .
REG3 Feedback-Sense Input. Connect directly to the REG3 output voltage. Output voltage is set by the serial
interface.
On/Off Input for REG6. Drive high to turn on. When enabled, the REG6 output activates. ON6 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1,
ON2, and ON6 are connected to SYS_EN.
Also known as VCC_USIM. Linear-regulator output. This voltage is programmable through the I 2 C interface to
0V, 1.8V, 2.5V, or 3.0V. The default voltage is 0V. REG6 is activated when ON6 is high.
Power Input to the V6 LDO. Typically connected to V1, but can also connect to IN.
REG1 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.
REG1 Switching Node. Connects to the REG1 inductor.
REG1 Power Input. Bypass to PG2 with a 4.7μF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and IN
must connect together externally.
On/Off Input for REG1. Drive high to turn on REG1. When enabled, the REG1 output soft-starts. ON1 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 connect to SYS_EN.
Sleep Input. SLP selects which regulators ON1 and ON2 turn on. SLP = high is normal operation (ON1 and
ON2 are the enables for the V1 and V2 DC-DC converters). SLP = low is sleep operation (ON1 and ON2 are
the enables for the V1 and V2 LDOs).
Dual-Mode, Dead-Battery Input. Connect DBI to IN to set the dead-battery falling threshold to 3.15V (no
resistors needed). Connect DBI to a resistor-divider for an adjustable DBI threshold.
Exposed Metal Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not
remove the requirement for proper ground connections to the appropriate ground pins.
16
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