- 您现在的位置：买卖IC网 > PDF目录16551 > MAX8588ETM+T (Maxim Integrated Products)IC PMIC HI EFF LOW IQ 48-TQFN PDF资料下载
参数资料
| 型号： | MAX8588ETM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 23/31页 |
| 文件大小： | 0K |
| 描述： | IC PMIC HI EFF LOW IQ 48-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页当前第23页第24页第25页第26页第27页第28页第29页第30页第31页
High-Efficiency, Low-I Q PMIC with
Dynamic Core for PDAs and Smartphones
A
t LOW
B
t HIGH
C
D
E
F
G
H
I
J
K
L
M
SCL
SDA
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO t BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMB DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
E = SLAVE PULLS SMB DATA LINE LOW
Figure 5. I 2 C-Compatible Serial-Interface Timing Diagram
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 5). A START condition from the master signals
the beginning of a transmission to the MAX8588. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see the
Acknowledge Bit section). The STOP condition frees
the bus.
When a STOP condition or incorrect address is detect-
ed, the MAX8588 internally disconnects SCL from the
serial interface until the next START condition, minimiz-
ing digital noise and feedthrough.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
every 8-bit data word. The receiving device always
generates ACK. The MAX8588 generates an ACK when
receiving an address or data by pulling SDA low during
the ninth clock period. Monitoring ACK allows for
Serial Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Table 3). When idle, the MAX8588
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected.
The LSB of the address word is the read/write (R/ W ) bit.
R/ W indicates whether the master is writing or reading
(RD/ W 0 = write, RD/ W 1 = read). The MAX8588 only
supports the SEND BYTE format; therefore, RD/ W is
required to be 0.
After receiving the proper address, the MAX8588
issues an ACK by pulling SDA low for one clock cycle.
The MAX8588 has two user-programmed addresses
(Table 3). Address bits A6 through A1 are fixed, while
A1 is controlled by SRAD. Connecting SRAD to GND
sets A1 = 0. Connecting ADD to IN sets A1 = 1.
V3 Output Ramp-Rate Control
When V3 is dynamically changed with the serial inter-
face, the output voltage changes at a rate controlled by
a capacitor (C RAMP ) connected from RAMP to ground.
The voltage change is a conventional RC exponential
described by:
Vo(t) = Vo(0) + dV(1 – exp(-t / (100k ? C RAMP )))
Table 3. Serial Address
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
SRAD
0
1
A7
0
0
A6
0
0
A5
1
1
A4
0
0
A3
1
1
A2
0
0
A1
0
1
A0
RD/ W
0
0
______________________________________________________________________________________
23
相关PDF资料 |
PDF描述 |
|---|---|
| SP1210R-681K | INDUCTOR PWR SHIELDED .680UH SMD |
| MAX1587AETL+T | IC POWER MANAGEMENT 40-TQFN |
| MAX1587CETL+T | IC POWER MANAGEMENT 40-TQFN |
| H3AWH-2036G | IDC CABLE - HSC20H/AE20G/HPL20H |
| SPD42R-563M | INDUCTOR PWR SHIELDED 56UH SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX858C/D | 功能描述:直流/直流开关转换器 DICE SALES DICE RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| MAX858CPA | 功能描述:直流/直流开关转换器 RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| MAX858CSA | 功能描述:直流/直流开关转换器 RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| MAX858CSA+ | 功能描述:直流/直流开关转换器 3.3/5/AdjV Step-Up DC/DC Converter RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| MAX858CSA+T | 功能描述:直流/直流开关转换器 3.3/5/AdjV Step-Up DC/DC Converter RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。