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| 型号： | MAX8632ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/29页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY DDR 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR |
| 输入电压： | 2 V ~ 28 V |
| 输出数： | 1 |
| 输出电压： | 1.8V，2.5V，0.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Pin Description (continued)
PIN
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
—
NAME
PGND2
VTT
VTTI
REFIN
FB
OUT
V IN
DH
LX
BST
DL
V DD
PGND1
GND
SKIP
AV DD
SHDN
TP0
EP
FUNCTION
Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad.
Termination Power-Supply Output. Connect VTT to VTTS to regulate to V REFIN / 2.
Power-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator
for DDR application.
External Reference Input. This is used to regulate the VTT and VTTR outputs to V REFIN / 2.
Feedback Input for Buck Output. Connect to AV DD for a +1.8V fixed output or to GND for a +2.5V fixed
output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output
voltage. FB regulates to +0.7V.
Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor.
OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in
Figure 8). OUT also serves as the buck output’s feedback input in fixed-output modes. When discharge
mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10 ? resistor
connected between OUT and GND. OUT also acts as the input to the VTT and VTTR UVLO detector.
Input-Voltage Sense Connection. Connect to input power source. V IN is used only to set the PWM’s on-
time one-shot timer. IN voltage range is from 2V to 28V.
High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.
External Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current
limit and the return supply of the DH driver.
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to Figure 8.
See the Boost-Supply Diode and Capacitor Selection (Buck) section.
Synchronous-Rectifier Gate-Driver Output. Swings from PGND to V DD .
Supply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to
PGND1 with a 1μF (min) ceramic capacitor.
Power Ground for Buck Controller. Connect PGND1 externally to the low-side FET’s source.
Analog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad.
Pulse-Skipping Control Input. Connect to AV DD for low-noise, forced-PWM mode. Connect to GND to
enable pulse-skipping operation.
Analog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage
with a series 10 ? resistor. Bypass to GND with a 1μF or greater ceramic capacitor.
Shutdown Control Input. Use to control buck output. A rising edge on SHDN clears the overvoltage-
and undervoltage-protection fault latches (see Tables 2 and 3). Connect to AV DD for normal operation.
This is a test pin. Must connect to GND externally.
Exposed pad. The exposed pad must be star-connected to GND and PGND2. See Special Layout
Considerations for LDO Section for more details.
10
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