参数资料
型号: MAX8654EVKIT+
厂商: Maxim Integrated Products
文件页数: 14/17页
文件大小: 0K
描述: EVAL KIT MAX8654, MAX8688
标准包装: 1
系列: *
12V, 8A 1.2MHz
Step-Down Regulator
output voltage divided by the rated output current. ESR
is the total equivalent series resistance (ESR) of the out-
put filtering capacitor. If there is more than one output
LX
L
V OUT
capacitor of the same type in parallel, the value of the
ESR in the above equation is equal to that of the ESR of
a single output capacitor divided by the total number of
MAX8654
C OUT
R3
R2
output capacitors.
C3
The high-switching frequency range of the MAX8654
allows the use of ceramic-output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
FB
R1
C1
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, f C , and the
zero cannot be used to compensate for the double pole
created by the output filtering inductor and capacitor.
The double pole produces a gain drop of 40dB and a
phase shift of 180° per decade. The error amplifier must
compensate for this gain drop and phase shift to
achieve a stable high-bandwidth, closed-loop system.
Therefore, use type 3 compensation as shown in Figure
3. Type 3 compensation possesses three poles and two
zeros with the first pole, f P1_EA , located at zero frequen-
cy (DC). Locations of other poles and zeros of the type
3 compensation are given by:
COMP
R4
C2
Figure 3. Type 3 Compensation Network
The zero-cross frequency of the closed loop, f C , should
be less than 20% of the switching frequency, f S . Higher
zero-cross frequency results in faster transient
response. It is recommended that the zero-cross fre-
quency of the closed loop should be chosen between
10% and 20% of the switching frequency. Once f C is
C 1 =
2 x π x R 3 x ( 1 + L ) × f C
f Z 1 _ EA =
f Z 2 _ EA =
f P 3 _ EA =
f P 2 _ EA =
1
2 π x R 1 x C 1
1
2 π x R 3 x C 3
1
2 π x R 1 x C 2
1
2 π x R 2 x C 3
chosen, C1 is calculated from the following equation:
1 . 5625 x V IN
R
R O
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the type 3
compensation less than the LC double-pole frequency
in order to provide adequate phase boost. Set the two
zero frequencies to 80% of the LC double-pole frequen-
cy. Hence:
The above equations are based on the assumptions
that C1>>C2 and R3>>R2 are true in most applica-
tions. Placements of these poles and zeros are deter-
R 1 =
1
0 . 8 x C 1
x
L x C O x ( R O + ESR )
R L + R O
mined by the frequencies of the double pole and ESR
zero of the power-transfer function. It is also a function
of the desired closed-loop bandwidth. The following
section outlines the step-by-step design procedure to
C 3 =
1
0 . 8 x R 3
x
L x C O x ( R O + ESR )
R L + R O
calculate the required compensation components for
the MAX8654.
Begin by setting the desired output voltage. The output
Set the second compensation pole, f P2_EA , at f Z_ESR
yields:
voltage is set using a resistor-divider from the output to
GND with FB at the center tap (R3 and R4 in Figure 3).
Calculate R4 as:
R 2 =
C O x ESR
C 3
C 2 =
R 4 =
0 . 6 × R 3
V OUT ? 0 . 6
Set the third compensation pole at the switching fre-
quency. Calculate C2 as follows:
1
π × R 1 × f S × 2
14
______________________________________________________________________________________
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