参数资料
型号: MAX8654EVKIT+
厂商: Maxim Integrated Products
文件页数: 8/17页
文件大小: 0K
描述: EVAL KIT MAX8654, MAX8688
标准包装: 1
系列: *
12V, 8A 1.2MHz
Step-Down Regulator
Pin Description
PIN
1, 2, 3, 34,
35, 36
4
5–8
9
10
11
12
13, 32
14
15
16
17
18
19
20
21
22–29
30, 33
31
NAME
PGND
VDL
IN
VP
VL
ILIM
FREQ
GND
REFIN
SS
COMP
FB
PWRGD
SYNCOUT
SYNC
BST
LX
N.C.
EN
EP
FUNCTION
Power Ground. All PGND pins are internally connected. Connect all PGND pins externally to the power
ground plane.
5V LDO Output. VDL supplies the gate-drive current to the internal MOSFETS, and charges the BST
capacitor. VDL requires at least a 2.2μF ceramic bypass capacitor to PGND.
Power-Supply Input. Input supply range is from 4.5V to 14V. Bypass with two 10μF and a 0.1μF ceramic
capacitors to PGND. See Figure 1.
Input of the Internal 5V LDO Regulator. Connect to IN if a 5V supply is not available. Connect to an external
5V supply to disable the internal 5V regulator.
3.3V LDO for Internal Chip Supply. Bypass with a 1μF ceramic capacitor to GND.
Current-Limit Adjust. Connect a resistor, R ILIM , from ILIM to GND. I ILIM = 1V / R ILIM . I ILIM determines the
LX current-limit trip point. See the Current Limit section for more details.
Oscillator Frequency Selection. Connect a resistor from FREQ to GND to set the internal oscillator
frequency. See the Frequency Select (FREQ) section for more details.
Analog Circuit Ground
External Reference Input. Connect to an external reference. FB regulates to the voltage applied to REFIN.
Connect REFIN to SS to use the internal 0.6V reference. REFIN is internally pulled to GND when the IC is in
shutdown mode.
Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. See the Soft-Start and REFIN
section for details.
Regulator Compensation. Connect the necessary compensation network from COMP to FB. COMP is
internally pulled to GND when the IC is in shutdown mode.
Feedback Input. Connect to the center tap of an external resistor-divider from the output to GND to set the
output voltage. See the Compensation Design section for more details.
Power-Good Output. Open-drain output that is high impedance when V FB ≥ 90% of V REFIN and V REFIN >
540mV. PWRGD is internally pulled low when the IC is in shutdown mode, or when V VDL , V IN , or V VL is
below the UVLO threshold, or the IC is in thermal shutdown.
Oscillator Output. The SYNCOUT output is 180 ° out-of-phase from the internal oscillator to facilitate running
a second regulator out-of-phase to reduce input ripple.
Synchronization Input. Synchronize to an external clock with a frequency of 250kHz to 1.2MHz. Connect
SYNC to GND to disable the synchronization function.
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.22μF ceramic capacitor.
Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the switched
side of the inductor. LX is high impedance when the IC is in shutdown mode.
Not Internally Connected
Enable Input. Logic input to enable/disable the MAX8654. Drive EN high to enable the IC. Drive EN low to
place the IC in a low-power shutdown mode.
Exposed Pad. Connect to a large PGND ground plane to optimize thermal performance. EP is internally
connected to GND and PGND.
8
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