参数资料
型号: MAX8731AETI+T
厂商: Maxim Integrated Products
文件页数: 20/32页
文件大小: 0K
描述: IC SMBUS LVL2 BATT CHRGR 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 充电管理
电池化学: 多化学
电源电压: 8 V ~ 26 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
SMBus Level 2 Battery Charger
with Remote Sense
SMBus Interface
The MAX8731A receives control inputs from the SMBus
interface. The MAX8731A uses a simplified subset of
the commands documented in System Management
Bus Specification V1.1, which can be downloaded from
www.smbus.org. The MAX8731A uses the SMBus
Read-Word and Write-Word protocols (Figure 3) to
communicate with the smart battery. The MAX8731A
performs only as an SMBus slave device with address
0b0001001_ (0x12) and does not initiate communica-
tion on the bus. In addition, the MAX8731A has two
identification (ID) registers (0xFE): a 16-bit device ID
register and a 16-bit manufacturer ID register (0xFF).
The data (SDA) and clock (SCL) pins have Schmitt-trig-
ger inputs that can accommodate slow edges. Choose
pullup resistors (10k Ω ) for SDA and SCL to achieve rise
times according to the SMBus specifications.
a) WRITE-WORD FORMAT
Communication starts when the master signals a
START condition, which is a high-to-low transition on
SDA, while SCL is high. When the master has finished
communicating, the master issues a STOP condition,
which is a low-to-high transition on SDA, while SCL is
high. The bus is then free for another transmission.
Figures 4 and 5 show the timing diagram for signals on
the SMBus interface. The address byte, command
byte, and data bytes are transmitted between the
START and STOP conditions. The SDA state changes
only while SCL is low, except for the START and STOP
conditions. Data is transmitted in 8-bit bytes and is
sampled on the rising edge of SCL. Nine clock cycles
are required to transfer each byte in or out of the
MAX8731A because either the master or the slave
acknowledges the receipt of the correct byte during the
ninth clock cycle. The MAX8731A supports the charger
commands as described in Table 4 .
S
SLAVE
ADDRESS
7 BITS
MSB LSB
W
1b
0
ACK
1b
0
COMMAND
BYTE
8 BITS
MSB LSB
ACK
1b
0
LOW DATA
BYTE
8 BITS
MSB LSB
ACK
1b
0
HIGH DATA
BYTE
8 BITS
MSB LSB
ACK P
1b
0
PRESET TO
0b0001001
ChargerMode() = 0x12
ChargeCurrent() = 0x14
D7 D0
D15 D8
ChargeVoltage() = 0x15
AlarmWarning() = 0x16
b) READ-WORD FORMAT
InputCurrent() = 0x3F
S
SLAVE
ADDRESS
7 BITS
MSB LSB
W
1b
0
ACK
1b
0
COMMAND
BYTE
8 BITS
MSB LSB
ACK
1b
0
S
SLAVE
ADDRESS
7 BITS
MSB LSB
R
1b
1
ACK
1b
0
LOW DATA
BYTE
8 BITS
MSB LSB
ACK
1b
0
HIGH DATA
BYTE
8 BITS
MSB LSB
NACK P
1b
1
Preset to
0b0001001
ChargerSpecInfo() = 0x11
ChargerStatus() = 0x13
PRESET TO
0b0001001
D7 D0
D15 D8
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 3 . SMBus Write-Word and Read-Word Protocols
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
20
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