参数资料
型号: MAX8742EAI+T
厂商: Maxim Integrated Products
文件页数: 22/34页
文件大小: 0K
描述: IC CNTRLR PWR SUP 28-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
应用: 控制器,笔记本电脑电源系统
输入电压: 4.2 V ~ 30 V
输出数: 2
输出电压: 3.3V,5V,2.5 V ~ 5.5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
500kHz Multi-Output Power-Supply Controllers
with High Impedance in Shutdown
0 . 025 × R ESR
R ESR < SENSE OUT
L PRIMARY =
Turns Ratio N =
Bypassing V+
Bypass the V+ input with a 4.7μF tantalum capacitor
paralleled with a 0.1μF ceramic capacitor, close to the
IC. A 10 Ω series resistor to V IN is also recommended.
Bypassing V L
Bypass the V L output with a 4.7μF tantalum capacitor
paralleled with a 0.1μF ceramic capacitor, close to the
device.
Output-Filter Capacitor Value
The output-filter capacitor values are generally deter-
mined by the ESR and voltage-rating requirements,
rather than actual capacitance requirements for loop sta-
bility. In other words, the low-ESR electrolytic capacitor
that meets the ESR requirement usually has more output
capacitance than is required for AC stability. Use only
specialized low-ESR capacitors intended for switching-
regulator applications, such as AVX TPS, Sanyo
POSCAP, or Kemet T510. To ensure stability, the capaci-
tor must meet both minimum capacitance and maximum
ESR values as given in the following equations:
V REF ( 1 + V OUT / V IN ( MIN ) )
C OUT >
V OUT × R SENSE × f
R × V
V REF
These equations are worst case, with 45° of phase mar-
gin to ensure jitter-free, fixed-frequency operation and
provide a nicely damped output response for zero to
full-load step changes. Some cost-conscious designers
may wish to bend these rules with less-expensive
capacitors, particularly if the load lacks large step
changes. This practice is tolerable if some bench test-
ing over temperature is done to verify acceptable noise
and transient response.
No well-defined boundary exists between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope does not quite sync up. Technically speaking,
this jitter (usually harmless) is unstable operation, since
the duty factor varies slightly. As capacitors with higher
ESRs are used, the jitter becomes more pronounced, and
the load-transient output-voltage waveform starts looking
ragged at the edges. Eventually, the load-transient wave-
form has enough ringing on it that the peak noise levels
exceed the allowable output-voltage tolerance. Note that
even with zero phase margin and gross instability pre-
sent, the output-voltage noise never gets much worse
than I PEAK ? R ESR (under constant loads).
The output-voltage ripple is usually dominated by the
filter capacitor’s ESR, and can be approximated as
I RIPPLE ? R ESR . There is also a capacitive term, so the
full equation for ripple in continuous-conduction mode
is V NOISE(P-P) = I RIPPLE ? [R ESR + 1/(2 ? π ? f ?
C OUT )]. In idle mode, the inductor current becomes
discontinuous, with high peaks and widely spaced
pulses, so the noise can actually be higher at light load
(compared to full load). In idle mode, calculate the out-
put ripple as follows:
V NOISE ( P - P ) = +
R SENSE
0 . 0003 × L × [ 1 / V OUT + 1 /( V IN - V OUT )]
R SENSE 2 × C OUT
Transformer Design
(for Auxiliary Outputs Only)
Buck-plus-flyback applications, sometimes called “cou-
pled-inductor” topologies, need a transformer to gener-
ate multiple output voltages. Performing the basic
electrical design is a simple task of calculating turns
ratios and adding the power delivered to the secondary
to calculate the current-sense resistor and primary
inductance. However, extremes of low input-output dif-
ferentials, widely different output loading levels, and
high turns ratios can complicate the design due to par-
asitic transformer parameters such as interwinding
capacitance, secondary resistance, and leakage induc-
tance. For examples of what is possible with real-
world transformers, see the Maximum V DD Output
Current vs. Input Voltage graph in the Typical Operating
Characteristics .
Power from the main and secondary outputs is com-
bined to get an equivalent current referred to the main
output voltage (see the Inductor Value section for para-
meter definitions). Set the current-sense resistor value
at 80mV / I TOTAL .
P TOTAL = the sum of the output power from all outputs
I TOTAL = P TOTAL / V OUT = the equivalent output current
referred to V OUT
V OUT ( V IN ( MAX ) - V OUT )
V IN ( MAX ) × f × I TOTAL × LIR
V SEC + V FWD
V OUT ( MIN ) + V RECT + V SENSE
22
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