参数资料
型号: MAX8753ETI+
厂商: Maxim Integrated Products
文件页数: 12/20页
文件大小: 0K
描述: IC DC-DC CONV TFT LCD 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
应用: 转换器,TFT,LCD
输入电压: 2.6 V ~ 5.5 V
输出数: 4
输出电压: 2.6 V ~ 13 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
TFT LCD DC-DC Converter with
Integrated Charge Pumps
V IN = 2.6V TO 5.5V
IN
L1
LX
D1 V MAIN (UP TO 13V)
DC-DC
DRV
REF-OK
LOGIC
R1
C MAIN1
C REF
REF
REF
GND
1.1V
CSN
CS
CSP
PGND
OSC
OSC
SC
EA
EAN
EAP
MAX8753
SLOPE
COMP
BUFFER
Gm
REF
FB
INTG
R2
R COMP
C COMP
C INTG
Figure 3. Step-Up Regulator Block Diagram
slope compensation signal is summed with the current-
sense and feedback signals.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
exceed the COMP voltage, the controller resets the flip-
flop, and turns off the MOSFET. Since the inductor cur-
rent is continuous, a transverse potential develops
across the inductor (L1) that turns on the diode (D1).
The voltage across the inductor then becomes the dif-
ference between the output voltage and the input volt-
age. This discharge condition forces the current
through the inductor to ramp back down, transferring
the energy stored in the magnetic field to the output
capacitor and the load. The MOSFET remains off for the
rest of the clock cycle.
Positive Charge-Pump Regulator
The positive charge-pump regulator is typically used to
generate the positive supply rail for the TFT LCD gate-
driver ICs (Figure 4). The output voltage is set with an
external resistive voltage-divider from its output to GND
with the midpoint connected to FBP. The positive
charge pump is a voltage tripler that accepts an input
voltage up to +13V and delivers a 20mA output up to
+28V without external switches or diodes.
During the first half-cycle (CLK is low), C1N pin is con-
nected to the ground, which allows V SUPP to charge up
the first flying capacitor C1 through diode D1. The
amount of charge transferred from V SUPP to C1 is
determined by the on-resistance of N1, which varies
according to the output of the feedback error amplifier.
During the second half-cycle (CLK is high), C1N is con-
nected to V SUPP through P1, level shifting C1 by V SUPP
volts. The on-resistance of P1 is also controlled by the
output of the feedback error amplifier. Meanwhile,
CLKB becomes low, pulling C2N to the ground. This
connects C1 in parallel with the second flying capacitor
12
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