参数资料
型号: MAX8753ETI+
厂商: Maxim Integrated Products
文件页数: 9/20页
文件大小: 0K
描述: IC DC-DC CONV TFT LCD 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
应用: 转换器,TFT,LCD
输入电压: 2.6 V ~ 5.5 V
输出数: 4
输出电压: 2.6 V ~ 13 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
TFT LCD DC-DC Converter with
Integrated Charge Pumps
Pin Description
PIN
1
2, 12, 20,
23
3
4
5
6
7
8
9
10
11
13
14
15
16, 17
18
19
21
22
24
25
26
27
28
NAME
SUPP
N.C.
C2N
C2P
OUTP
INTG
FB
FBP
FBL
OUTL
IN
GND
REF
FBN
I.C.
C3P
SUPN
LX
PGND
DLP
SHDN
LCDON
C1N
C1P
FUNCTION
Positive Charge-Pump Supply Voltage. Bypass to PGND with a 0.1μF capacitor.
No connection. Not internally connected.
Negative Terminal of Flying Capacitor C2
Positive Terminal of Flying Capacitor C2
Positive Charge-Pump Output
Step-Up Regulator Integrator Output. Connect a 470pF capacitor from INTG to GND.
Step-Up Converter Feedback Input. Regulates to 1.245V (nominal). Connect a resistor-divider from the
output (V MAIN ) to FB to analog ground (GND). Place the resistor-divider within 5mm of FB.
Positive Charge-Pump Feedback Input. Regulates to 1.25V (nominal). Connect a resistor-divider from the
output (OUTP) to FBP to analog ground (GND). Place the resistor-divider within 5mm of FBP.
Logic Linear Regulator Dual-Mode Feedback Input. Connect FBL to GND to select the 2.5V preset linear
regulator output voltage (OUTL). Connect FBL to the center tap of a resistive voltage-divider between
OUTL and GND to set an adjustable output voltage. In adjustable mode, FBL is regulated at 1.25V nominal.
Place the resistive divider within 5mm of FBL.
Logic Linear Regulator Output. Output of the 2.5V or adjustable linear regulator. Bypass to GND with a
10μF (min) capacitor.
Supply Input. +2.6V to +5.5V input range. Supply input for the IC and input for the internal logic linear
regulator. Bypass to GND with a 0.1μF capacitor within 5mm of the IC pins.
Analog Ground. Connect to power ground (PGND) underneath the IC.
Internal Reference Output. Bypass REF to GND with a 0.22μF (min) capacitor. REF can supply up to 50μA
to an external load.
Negative Charge-Pump Feedback Input. Connect a resistor-divider from the output (OUTN) to FBN to the
reference output (REF). Place the resistor-divider within 5mm of FBN.
Internally Connected. Make no connection to this pin.
Positive Terminal of Flying Capacitor C3
Negative Charge-Pump Supply Voltage. Bypass to PGND with a 0.1μF capacitor.
Power MOSFET n-Channel Drain and Switching Node. Connect the inductor and catch diode to LX and
minimize the trace area for lowest EMI.
Power Ground. PGND is the source of the main boost/n-channel power MOSFET. Connect PGND to the
output capacitor ground terminals through a short, wide PC board trace.
Positive Charge-Pump Startup Delay Input. Connect a capacitor from DLP to GND to set the delay time. A
5μA current source charges C DLP . DLP is pulled to GND by a 20 ? switch when shut down.
Active-Low Shutdown Control Input. All outputs are disabled when SHDN is low. When SHDN is high, REF
and OUTL are enabled and the LCD supplies can be enabled if LCDON is high.
LCD Supply Enable Input. All LCD supply outputs (MAIN, OUTN, and OUTP) are disabled when LCDON is
low. REF and OUTL are unaffected by LCDON.
Negative Terminal of Flying Capacitor C1
Positive Terminal of Flying Capacitor C1
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