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参数资料
| 型号： | MAX8831EWE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVR WHITE BCKLGT 16-WLP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 拓扑： | 线性（LDO），PWM，升压（升压） |
| 输出数： | 5 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 1.8MHz ~ 2.2MHz |
| 电源电压： | 1.6 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 供应商设备封装： | 16-WLP（2x2） |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | MAX8831EWE+TDKR |
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High-Efficiency, White LED Step-Up Converter
with I 2 C Interface in 2mm x 2mm WLP
SDA
t SU,DAT
t SU,STA
t BUF
t LOW
t HD,DAT
t HD,STA
t SU,STO
SCL
t HD,STA
t HIGH
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
STOP
CONDITION
Figure 5. I 2 C Interface Timing Diagram
SCL output. Each transmission consists of a START
condition (Figure 6) sent by a master, followed by the
MAX8831 7-bit slave address plus a R/W bit, a register
SDA
SCL
address byte, 1 or more data bytes, and finally a STOP
condition (Figures 5 and 6).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. The master signals the beginning of a trans-
S
START CONDITION
Figure 6. I 2 C START and STOP Conditions
P
STOP CONDITION
mission with a START (S) condition by transitioning
SDA from high to low while SCL is high. When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning the SDA from low
to high while SCL is high. The bus is then free for
another transmission (Figure 6).
I 2 C Interface
Bit Transfer
The
and
MAX8831 operates as an I 2 C slave that receives
sends data through an I 2 C-compatible, 2-wire
One data bit is clocked onto SDA on the falling edge of
SCL and is read on the rising edge of SCL. The data on
interface. The LED1–LED5 current settings, ramp and
blink-rate timers, and other configuration parameters
are set using the I 2 C serial interface. See the register
definitions for more details.
The interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from
the MAX8831, and generates the SCL clock that syn-
chronizes the data transfer (Figure 5). The MAX8831
SDA line operates as both an input and an open-drain
output. A pullup resistor, typically 4.7k Ω , is required on
SDA. The MAX8831 SCL line operates only as an input.
A pullup resistor, typically 4.7k Ω , is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
the SDA line must remain stable while SCL transitions
(Figure 7).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX8831, the
MAX8831 generates the acknowledge bit because it is
the recipient. When the MAX8831 is transmitting to the
master, the master generates the acknowledge bit
because it is the recipient.
______________________________________________________________________________________
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