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参数资料
| 型号： | MAX8833ETJ+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A DL 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 3.24 V |
| 输入电压： | 2.35 V ~ 3.6 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 1MHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
Dual, 3A, 2MHz Step-Down Regulator
The power-good, open-drain output for regulator 2
(PWRGD2) is high impedance when V SS2 ≥ 0.54V and
V FB2 ≥ 0.9 x V SS2 . PWRGD2 is low when V SS2 < 0.54V,
THERM
EN2 is low, V VDD or V IN2 is below V UVLO , the thermal-over-
IN1
SHDN
load protection is activated, or when V FB2 < 0.9 x V SS2 .
External Reference Input (REFIN)
The MAX8833 has an external reference input. Connect
RRUVB
UVLO
UVLO
TLIM
REG1 ON
an external reference between 0 and V VDD - 1.6V to
REFIN to set the FB1 regulation voltage. To use the inter-
nal 0.6V reference, connect REFIN to SS1. When the IC
is shut down, REFIN is pulled to GND through 335 Ω .
BIAS
GEN
V DD
Startup and Sequencing
The MAX8833 features separate enable inputs (EN1
and EN2) for the two regulators. Driving EN_ high
enables the corresponding regulator; driving EN_ low
turns the regulator off. Driving both EN1 and EN2 low
EN1
EN2
UVLO
UVLO
REF
REF
RDY
REG2 ON
UVLO
RRUVB
puts the IC in low-power shutdown mode, reducing the
supply current typically to 30nA. The MAX8833 regula-
RRUVB
TLIM
tors power up when the following conditions are met
(see Figure 2):
?
EN_ is logic-high.
IN2
THERM
SHDN
?
?
?
?
V VDD is above the UVLO threshold.
V IN_ is above the UVLO threshold.
The internal reference is powered.
The IC is not in thermal overload (T J < +165°C).
Figure 2. Startup Control Diagram
soft-start time. See the Setting the Soft-Start Time sec-
tion to select the SS2 capacitor for the desired soft-start
Once these conditions are met, the MAX8833 begins
soft-start. FB2 regulates to the voltage at SS2. During
soft-start, the SS2 capacitor is charged with a constant
8μA current source so that its voltage ramps up for the
time. FB1 regulates to the voltage at REFIN. Connect
REFIN to SS1 to use the internal reference with soft-
start time set independently by the SS1 capacitor (see
Figure 3a).
EN1
OUT1
PWRGD1
EN2
OUT2
PWRGD2
10k Ω
10k Ω
PWRGD1
V DD
PWRGD2
SS1
EN1
EN2
SS2
REFIN
EN1
EN2
Figure 3a. Startup and Sequencing Options—Two Independent Output Startup and Shutdown Waveforms
10
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