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参数资料
| 型号： | MAX8833ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A DL 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 3.24 V |
| 输入电压： | 2.35 V ~ 3.6 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 1MHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
Dual, 3A, 2MHz Step-Down Regulator
V RIPPLE ( C ) =
f P 1 _ LC = f P 2 _ LC =
2 π × L × C O × ? O
? R O + R L ?
Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC convert-
er. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Calculate the output-voltage ripple
due to the output capacitance, ESR, and ESL as:
V RIPPLE = V RIPPLE ( C ) + V RIPPLE ( ESR ) + V RIPPLE ( ESL )
where the output ripple due to output capacitance,
ESR, and ESL is:
I P ? P
8 × C OUT × f S
V RIPPLE ( ESR ) = I P ? P × ESR
After a short time, the controller responds by regulating
the output voltage back to its predetermined value. The
controller response time depends on the closed-loop
bandwidth. A higher bandwidth yields a faster
response time, preventing the output from deviating fur-
ther from its regulating value. See the Compensation
Design and Safe-Starting into a Prebiased Output sec-
tions for more details.
Compensation Design
The power-stage transfer function consists of one dou-
ble pole and one zero. The double pole is introduced
by the output filtering inductor, L, and the output filter-
ing capacitor, C O . The ESR of the output filtering
capacitor determines the zero. The double pole and
zero frequencies are given as follows:
1
? R + ESR ?
?
V RIPPLE ( ESL ) = × ESL
I P ? P
t ON
f Z _ ESR =
1
2 π × ESR × C O
where R L is equal to the sum of the output inductor’s
V RIPPLE ( ESL ) = × ESL
or:
I P ? P
t OFF
DC resistance and the internal switch resistance,
R DS(ON) . A typical value for R DS(ON) is 35m Ω . R O is the
output load resistance, which is equal to the rated out-
put voltage divided by the rated output current. ESR is
the total ESR of the output-filtering capacitor. If there is
I P ? P = IN OUT × OUT
whichever is greater.
It should be noted that the above ripple voltage compo-
nents add vectrorially rather than algebraically, thus
making V RIPPLE a conservative estimate.
The peak inductor current (I P-P ) is:
V ? V V
f S × L V IN
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an eval-
uation circuit. A smaller ripple current results in less out-
put-voltage ripple. Since the inductor ripple current is a
function of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capaci-
tors for low ESR and low ESL at the switching frequency
of the converter. The low ESL of ceramic capacitors
makes ripple voltages due to ESL negligible.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
more than one output capacitor of the same type in par-
allel, the value of the ESR in the above equation is
equal to that of the ESR of a single-output capacitor
divided by the total number of output capacitors.
The high-switching-frequency range of the MAX8833
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer-function zero is high-
er than the unity-gain crossover frequency, f C , and the
zero cannot be used to compensate for the double pole
created by the output filtering inductor and capacitor.
The double pole produces a gain drop of 40dB and a
phase shift of 180° per decade. The error amplifier
must compensate for this gain drop and phase shift to
achieve a stable high-bandwidth closed-loop system.
Therefore, use type III compensation as shown in
Figure 4. Type III compensation possesses three poles
and two zeros with the first pole, f P1_EA , located at 0Hz
(DC). Locations of other poles and zeros of type III
compensation are given by:
instantly changes by ESR x Δ I LOAD . Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor values.
f Z 1 _ EA =
1
2 π × R 7 × C 9
14
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