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参数资料
| 型号： | MAX8833ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A DL 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 3.24 V |
| 输入电压： | 2.35 V ~ 3.6 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 1MHz ~ 2MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
Dual, 3A, 2MHz Step-Down Regulator
2 π × f C × R 4 × ? 1 + L ?
f Z 2 _ EA =
1
2 π × R 4 × C 11
C 9 =
2 . 5 × V IN
? R ?
? R O ?
f P 2 _ EA =
f P 3 _ EA =
1
2 π × R 7 × C 10
1
2 π × R 8 × C 11
where V IN is the input voltage in volts, f C is the
crossover frequency in Hertz, R4 is the upper feedback
resistor (in ohms), R L is the sum of the inductor resis-
tance and the internal switch on-resistance, and R O is
the output load resistance (V OUT /I OUT ).
Due to the underdamped nature of the output LC double
These equations are based on the assumptions that C9
>> C10, and R4 >> R8, which are true in most applica-
tions. Placement of these poles and zeros is deter-
mined by the frequencies of the double pole and ESR
zero of the power stage transfer function. It is also a
pole, set the two zero frequencies of the type III com-
pensation less than the LC double-pole frequency to
provide adequate phase boost. Set the two zero fre-
quencies to 80% of the LC double-pole frequency.
Hence:
function of the desired closed-loop bandwidth. Figure 5
shows the pole zero cancellations in the type III com-
pensation design.
R 7 =
1
0 . 8 × C 9
×
L × C O × ( R O + ESR )
R L + R O
The following section outlines the step-by-step design
procedure to calculate the required compensation com-
ponents. Begin by setting the desired output voltage as
C 11 =
1
0 . 8 × R 4
×
L × C O × ( R O + ESR )
R L + R O
described in the Setting the Output Voltage section.
The crossover frequency f C (or closed-loop, unity-gain
bandwidth of the regulator) should be between 10%
Set the third compensation pole, f P3_EA , at f Z_ESR ,
which yields:
and 20% of the switching frequency, f S . A higher
crossover frequency results in a faster transient
response. Too high of a crossover frequency can result
R 8 =
C O × ESR
C 11
in instability. Once f C is chosen, calculate C9 (in
farads) from the following equation:
OPEN-LOOP GAIN
COMPENSATION TRANSFER FUNCTION
THIRD POLE
DOUBLE POLES
SECOND POLE
POWER-STAGE TRANSFER FUNCTION
FIRST AND SECOND ZEROS
FREQUENCY
Figure 5. Pole Zero Cancellations in Compensation Design
______________________________________________________________________________________
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