参数资料
型号: MAX8982EWO+T
厂商: Maxim Integrated Products
文件页数: 34/73页
文件大小: 0K
描述: IC PWR MGMT ICERA E400 42WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
应用: 电源,ICERA E400,E450
输入电压: 4.1 V ~ 5.5 V
输出数: 13
输出电压: 可编程
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 42-WFBGA,WLCSP
供应商设备封装: 42-WLP
包装: 带卷 (TR)
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 3. External Componen t List for Figure 2
LOCATION
IN1A, IN1B
IN3
IN4
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
VSIM (OUT7)
OUT9
V DDA , V DDB
BUCK1 for BB Core
BUCK2 for BB System IO
LX1
LX2
REFBP
EN
Any Bump Required to Pass 8kV
Module Level ESD
EXTERNAL COMPONENTS
22 F F
2.2 F F
4.7 F F
1.0 F F
1.0 F F
2.2 F F
1.0 F F
1.0 F F
1.0 F F
2.2 F F
Total capacitance R total output capacitance
for LDO1, LDO2, LDO3, LDO5, LDO6, and
VSIM.
2.2 F F
2.2 F F
1 F H to 4.7 F H
1 F H to 4.7 F H
0.1 F F
A pulldown resistor, if necessary
0.1 F F
NOTES
Buck stability
Input for LDO4 and LDO9
Connect to IN1A and IN1B
LDO compensation and load transient
response
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
All LDOs stability. Connect V DDA and
V DDB to IN1A and IN1B.
For low noise, 1.2A continuous load
For low noise
2.2 F H recommended (Table 60)
1.0 F H recommended (Table 60)
Noise filter
Absorb ESD energy
Note: Input/output capacitance should be as close as possible to the IC. All capacitors are ceramic X5R or X7R, unless otherwise noted.
Detailed Description
Power-On/Off Control
The power-on/off state diagram is shown in Figure 3.
When the IN1_ supply voltage is valid and EN is high,
the default power supplies turn on in sequence (Figure
4). Once powered up, any step-down or LDO output can
be enabled or disabled through I 2 C, or they can be pro-
grammed to be controlled by the PWR_REQ logic input.
PWR_REQ
PWR_REQ is a control input from baseband chipset used
to enable/disable specified regulators.
After power-up, when PWR_REQ goes logic-high, any
step-down or LDO output programmed for PWR_REQ
control is enabled in a predefined sequence. The regulators
are powered up in four groups as shown in Figure 5. See the
following for the regulators belonging to each group. When
PWR_REQ goes logic-low, all regulators programmed for
PWR_REQ control are turned off simultaneously.
34
Any regulator that is set to on or off though I 2 C is not
affected by PWR_REQ, except for BUCK1. The pro-
grammed values in BUCK1DVS1 and BUCK1DVS2 are
reset to their defaults when PWR_REQ goes low even in
normal operation.
Group A: BUCK3 (MAX8982A/MAX8982P only)
LDO2 (default is PWR_REQ On mode)
BUCK2
Group B: LDO1 (default is PWR_REQ On mode)
LDO3
BUCK4 (MAX8982A/MAX8982P only)
Group C: LDO6 (default is PWR_REQ On mode)
LDO5
LDO7
LDO8 (MAX8982A/MAX8982P only)
Group D: BUCK1 (default is PWR_REQ On mode)
LDO4 (default is PWR_REQ On mode)
LDO9
Maxim Integrated
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