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| 型号： | MAX8982EWO+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 40/73页 |
| 文件大小： | 0K |
| 描述： | IC PWR MGMT ICERA E400 42WLP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 应用： | 电源，ICERA E400，E450 |
| 输入电压： | 4.1 V ~ 5.5 V |
| 输出数： | 13 |
| 输出电压： | 可编程 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 42-WFBGA，WLCSP |
| 供应商设备封装： | 42-WLP |
| 包装： | 带卷 (TR) |
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MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
SDA
SCL
DATA LINE STABLE DATA VALID
Figure 12. I 2 C Bit Transfer
RESET SIGNAL to B/B Chipset
The ICs include one dedicated reset output called
RESET . This is the reset signal for the core and RTB
(real-time block) in baseband. RESET goes high after the
ICs’ power-up sequence is complete. RESET is pulled
low when the ICs are shut down (due to input supply out
of range or EN goes low).
I 2 C Serial Interface
An I 2 C-compatible, 2-wire serial interface is used for
regulator on/off control, setting output voltages, LED
control, and other functions. See Table 5 for the com-
plete register map.
CHANGE OF DATA ALLOWED
SDA
SCL
The I 2 C serial bus consists of a bidirectional serial-data
line (SDA) and a serial-clock line (SCL). I 2 C is an open-
drain bus. SDA and SCL require pullup resistors (500 I
START
CONDITION
STOP
CONDITION
or greater). Optional 24 I resistors in series with SDA and
SCL help to protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
Bit Transfer
One data bit is transferred for each SCL clock cycle. The
data on SDA must remain stable during the high portion of
the SCL clock pulse (Figure 12). Changes in SDA while SCL
is high are control signals (START and STOP conditions).
START and STOP Conditions
Each transmit sequence is framed by a START (S) condi-
tion and a STOP (P) condition. Each packet is 9 bits long; 8
bits of data followed by the acknowledge bit. The ICs sup-
port data transfer rates with a SCL frequency up to 400kHz.
40
Figure 13. START and STOP Conditions
Both SDA and SCL remain high when the bus is not
busy. The master device initiates communication by
issuing a START condition. A START condition is a
high-to-low transition of SDA, while SCL is high. A STOP
condition is a low-to-high transition of the data line while
SCL is high (Figure 13).
A START condition from the master signals the begin-
ning of a transmission to the ICs. The master terminates
transmission by issuing a not acknowledge followed by a
STOP condition. See the Acknowledge section for more
information. The STOP condition frees the bus. To issue
a series of commands to the slave, the master can issue
Maxim Integrated
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相关代理商/技术参数 |
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|---|---|
| MAX8982MEWO+T | 功能描述:PMIC 解决方案 PMIC for ICERA E400/E450 Platform RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8982PEWO+T | 功能描述:PMIC 解决方案 PMIC for ICERA E400/E450 Platform RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8982XEWO+T | 制造商:Maxim Integrated Products 功能描述:POWER MANAGEMENT IC FOR ICERA E400/E450 PLATFORM-MINI CARD - Tape and Reel |
| MAX8986EVKIT+ | 制造商:Maxim Integrated Products 功能描述:PMIC FOR BROADCOM BB ATHENA - Boxed Product (Development Kits) |
| MAX8986EWG+ | 制造商:Maxim Integrated Products 功能描述:POWER MANAGEMENT IC FOR CELL PHONE |
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