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| 型号： | MAX9218ETM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/15页 |
| 文件大小： | 0K |
| 描述： | IC DESERIALIZER LVDS 48-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 解串器 |
| 数据速率： | 700Mbps |
| 输入类型： | LVDS |
| 输出类型： | LVCMOS |
| 输入数： | 1 |
| 输出数： | 27 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
4
_______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at
≤ 0.3V or ≥ VCC - 0.3V. PWRDWN is ≤ 0.3V.
Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5: CL includes probe and test jig capacitance.
AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to 3.6V, CL = 8pF, PWRDWN = high, differential input voltage
VID = 0.1V to 1.2V, input common-mode voltage
VCM =
VID/2 to VCC - VID/2, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V, VCM =
1.2V, TA = +25°C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFCLK TIMING REQUIREMENTS
Period
tT
28.57
333.00
ns
Frequency
fCLK
3
35
MHz
Frequency Variation
ΔfCLK
REFCLK to serializer PCLK_IN
-2.0
+2.0
%
Duty Cycle
DC
40
50
60
%
Transition Time
tTRAN
20% to 80%
6
ns
SWITCHING CHARACTERISTICS
RNG1, RNG0 = high
3.2
4.4
Output Rise Time
tR
Figure 3
RNG1, RNG0 both not high
simultaneously
3.8
5.5
ns
RNG1, RNG0 = high
2.7
4.5
Output Fall Time
tF
Figure 3
RNG1, RNG0 both not high
simultaneously
3.6
5.3
ns
PCLK_OUT High Time
tHIGH
Figure 4
0.4 x
tT
0.45 x
tT
0.6 x
tT
ns
PCLK_OUT Low Time
tLOW
Figure 4
0.4 x
tT
0.45 x
tT
0.6 x
tT
ns
Data Valid Before PCLK_OUT
tDVB
Figure 5
0.35 x tT
0.4 x tT
ns
Data Valid After PCLK_OUT
tDVA
Figure 5
0.35 x tT
0.4 x tT
ns
Input-to-Output Delay
tDELAY
Figure 6
2.575 x
tT +
8.5
2.725 x
tT +
12.8
ns
PLL Lock to REFCLK
tPLLREF
Figure 7
16385 x
tT
ns
Power-Down Delay
tPDD
Figure 7
100
ns
Output Enable Time
tOE
Figure 8
30
ns
Output Disable Time
tOZ
Figure 9
30
ns
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