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参数资料
| 型号： | MAX9250GCM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC DESERIALIZER LVDS 48-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 功能： | 解串器 |
| 数据速率： | 840Mbps |
| 输入类型： | LVDS |
| 输出类型： | LVCMOS |
| 输入数： | 1 |
| 输出数： | 27 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
_______________________________________________________________________________________
7
Pin Description
PIN
MAX9248
MAX9250
NAME
FUNCTION
11
R/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT
for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a
falling latch edge. Internally pulled down to GND.
2
RNG1
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internally pulled down to GND.
33
VCCLVDS
LVDS Supply Voltage. Bypass to LVDSGND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
4
IN+
Noninverting LVDS Serial-Data Input
5
IN-
Inverting LVDS Serial-Data Input
6
LVDSGND
LVDS Supply Ground
7
PLLGND
PLL Supply Ground
88
VCCPLL
PLL Supply Voltage. Bypass to PLLGND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
9
RNG0
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internal pulldown to GND.
10
GND
Digital Supply Ground
11
VCC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to
GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible with
the smallest value capacitor closest to the supply pin.
12
REFCLK
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within
±2% of the
serializer PCLK_IN frequency. Internally pulled down to GND.
13
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
14
—
SS
LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of PCLK_OUT and
output data relative to PCLK_IN. Drive SS high for 4% spread and pull low for 2% spread.
15–23
CNTL_OUT0–
CNTL_OUT8
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the
rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held
at the last state when DE_OUT is high.
24
DE_OUT
LVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active. Low
indicates CNTL_OUT[8:0] are active.
25, 37
VCCOGND
Output Supply Ground
26, 38
VCCO
Output Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9251 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX9252 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX9253 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| MAX9254 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| MAX9254EUM | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
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