参数资料
型号: MAX9250GCM+T
厂商: Maxim Integrated Products
文件页数: 19/20页
文件大小: 0K
描述: IC DESERIALIZER LVDS 48-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
功能: 解串器
数据速率: 840Mbps
输入类型: LVDS
输出类型: LVCMOS
输入数: 1
输出数: 27
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
8
_______________________________________________________________________________________
Functional Diagram
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC
BALANCE/
DECODE
1
0
RGB_OUT
LOCK
PWRDWN
SS
PCLK_OUT
DE_OUT
CNTL_OUT
SSPLL
FIFO
RNG[0:1]
R/F
RNG[0:1]
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC
BALANCE/
DECODE
1
0
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
R/F
MAX9250
MAX9248
Pin Description (continued)
PIN
MAX9248
MAX9250
NAME
FUNCTION
27
LOCK
LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
28
PCLK_OUT
LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
29–36,
39–48
29–36,
39–48
RGB_OUT0–
RBG_OUT7,
RGB_OUT8–
RGB_OUT17
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are
latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high,
and are held at the last state when DE_OUT is low.
14
OUTEN
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving
low places the single-ended outputs in high impedance except LOCK. Internally pulled
down to GND.
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