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参数资料
| 型号： | MAX9315EUP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA BUFF MUX 2:5 20TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 扇出缓冲器（分配），多路复用器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:5 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HSTL，LVECL，LVPECL |
| 输出： | LVECL，LVPECL |
| 频率 - 最大： | 1.5GHz |
| 电源电压： | 2.25 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
VEE connected to ground, the outputs are LVPECL. The
outputs are LVECL when VCC is connected to ground
and VEE is connected to a negative supply.
Input Bias Resistors
When the inputs are open, the internal bias resistors set
the inputs to low state. The inverting inputs (CLK0 and
CLK1) are each biased with a 75k
pullup to VCC and a
75k
pulldown to VEE. The noninverting inputs (CLK0
and CLK1) are each biased with a 75k
pulldown to VEE.
Differential Clock Input Limits
The maximum magnitude of the differential signal
applied to the clock input is 3.0V or VCC - VEE, whichev-
er is less. This limit also applies to the difference
between any reference voltage input and a single-ended
input. Specifications for the high and low voltages of a
differential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously.
Single-Ended Clock Input and VBB
The differential clock inputs can be configured to
accept single-ended inputs. This is accomplished by
connecting the on-chip reference voltage, VBB, to the
inverting or noninverting input of a differential input as a
reference. For example, the differential CLK0, CLK0
input is converted to a noninverting, single-ended input
by connecting VBB to CLK0 and connecting the single-
ended input signal to CLK0. Similarly, an inverting con-
figuration is obtained by connecting VBB to CLK0 and
connecting the single-ended input to CLK0. With a dif-
ferential input configured as single ended (using VBB),
the single-ended input can be driven to VCC and VEE or
with a single-ended LVPECL/LVECL signal. Note that
single-ended input must be at least VBB ±100mV or a
differential input of at least 100mV to switch the outputs
to the VOH and VOL levels specified in the DC Electrical
Characteristics table.
If VBB is used, the supply must be in the VCC - VEE =
+2.725V to +3.8V range because one of the inputs
must be VEE + 1.2V or higher for proper input stage
operation. VBB must be at least VEE + 1.2V because it
becomes the high-level input when the other (single-
ended) input swings below it. Therefore, minimum VBB
= VEE + 1.2V. The minimum VBB output of the
MAX9315 is VCC - 1.525V. Substituting the minimum
VBB output into VBB = VEE + 1.2V results in a minimum
supply of +2.725V. Rounding up to standard supplies
gives the single-ended operating supply range of VCC -
VEE = +3.0V to +3.8V.
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference
is not used, leave it open. The VBB reference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use VBB only for inputs that are on the same
device as the VBB reference.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel as
close to the device as possible, with the 0.01F capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBB ref-
erence output, bypass it with a 0.01F ceramic capaci-
tor to VCC (if the VBB reference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9315. Connect high-frequency input
and output signals with 50
characteristic impedance
traces. Minimize the number of vias to prevent imped-
ance discontinuities. Reduce reflections by maintaining
the 50
characteristic impedance through cables and
connectors. Reduce skew within a differential pair by
matching the electrical length of the traces.
Output Termination
Terminate outputs with 50
to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 616
PROCESS: Bipolar
MAX9315
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
_______________________________________________________________________________________
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9315EUP-TG068 | 制造商:Maxim Integrated Products 功能描述:1:5 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND - Rail/Tube |
| MAX9315EVKIT | 功能描述:时钟驱动器及分配 Evaluation Kit for the MAX9315 MAX9316 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9316AEWP | 功能描述:时钟驱动器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9316AEWP-T | 功能描述:时钟驱动器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9316EUP | 制造商:Maxim Integrated Products 功能描述:1:5 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND - Rail/Tube |
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