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参数资料
| 型号： | MAX9325EQI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA BUFF MUX 2:8 28-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 39 |
| 类型： | 扇出缓冲器（分配），多路复用器，数据 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | HSTL，LVECL，LVPECL |
| 输出： | LVECL，LVPECL |
| 频率 - 最大： | 700MHz |
| 电源电压： | 2.375 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 管件 |
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________
5
AC ELECTRICAL CHARACTERISTICS—QFN Package
((VCC - VEE) = 2.375V to 3.8V, RL = 50 ±1% to VCC - 2V, fIN ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
are at (VCC - VEE) = 3.3V, VIH = (VCC - 1V), VIL = (VCC - 1.5V).) (Note 7)
-40
°C
+25
°C
+85
°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Differential
Input-to-Output
Delay
tPLHD
tPHLD
Figure 2
250
575
298
553
309
576
ps
Single-Ended
Input-to-Output
Delay
tPLH
tPHL
Figure 3 (Note 8)
253
581
310
586
324
606
ps
Output-to-
Output Skew
tSKOO
(Note 9)
50
ps
Part-to-Part
Skew
tSKPP
Differential input
(Note 10)
192
215
218
ps
Added Random
Jitter
tRJ
fIN = 0.5GHz
clock pattern
(Note 11)
1.5
psRMS
Added
Deterministic
Jitter
tDJ
fIN = 1.0Gbps,
2E
23 - 1 PRBS
pattern (Note 11)
95
psP-P
Switching
Frequency
fMAX
VOH - VOL
≥
300mV clock
pattern
1.5
GHz
Output Rise/Fall
Time (20% to
80%)
tR, tF
Figure 2
97
411
104
210
111
232
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters production tested at TA = +25°C and guaranteed by design over the full operating temperature range.
Note 4:
Single-ended input operation using VBB is limited to (VCC - VEE) = 3.0V to 3.8V.
Note 5:
Use VBB only for inputs that are on the same device as the VBB reference.
Note 6:
All pins open except VCC and VEE.
Note 7:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:
Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal.
Note 9:
Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal.
Note 10: Measured between outputs of different parts under identical condition for same-edge transition.
Note 11: Device jitter added to the input signal. Differential input signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9325EQI+ | 功能描述:时钟驱动器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9325EQI+T | 功能描述:时钟驱动器及分配 LVPECL/LVECL/HSTL Clock & Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MAX9325EVKIT | 制造商:Maxim Integrated Products 功能描述:2:8 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND DATA DRIVER - Boxed Product (Development Kits) |
| MAX9326EGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX9326EQI | 制造商:Maxim Integrated Products 功能描述:1:9 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND - Rail/Tube |
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