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参数资料
| 型号： | MAX9471ETP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/13页 |
| 文件大小： | 0K |
| 描述： | IC MULTI-PURPOSE CLK GEN 20-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 时钟发生器 |
| PLL： | 是 |
| 输入： | LVCMOS，晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 供应商设备封装： | 20-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
Device Address
The default I2C address for the MAX9471 is factory set to
1100111. Contact factory for different addresses.
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. The active master signals the beginning of a
transmission with a START (S) condition by transitioning
SDA from high to low while SCL is high. When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Data Transfer and ACK
Following the START condition, each SCL clock pulse
transfers 1 bit. Between a START and a STOP, multiple
bits are transferred on the 2-wire bus. The first 7 bits are
for the device address. Bit 8 indicates the writing (low)
or reading (high) operation (R/
W). Bit 9 is the ACK for
the address and operation type. The next 8 bits (bit 10
to bit 17) form the content byte. The next bit, bit 18, is
the ACK for the content byte. The master always trans-
fers the first 8 bits (address + R/
W). The slave
(MAX9471) may receive a content byte from the bus or
transfer a content byte to the bus. The ACK bits are
transmitted by the address or content recipient. A low-
ACK bit indicates a successful transfer; otherwise, a
high-ACK bit indicates an unsuccessful transfer. More
content bytes can be continuously transferred until the
master sends a STOP. For the MAX9471 data writing,
after the 9 bits with the slave ID, R/
W, and ACK, 1 data
byte is sent to the MAX9471 from the master. Figure 4
shows the structure of the data transfer. Figure 5 shows
CLK_ rise and fall times.
MAX9471/MAX9472
Multiple-Output Clock Generators with
Dual PLLs and OTP
_______________________________________________________________________________________
9
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
Figure 3. START and STOP Diagram
A
P
A
W
S
SLAVE ADDRESS
MASTER-WRITE DATA STRUCTURE
MASTER-READ DATA STRUCTURE
DATA
AA
P
A
R
S
SLAVE ADDRESS
DATA
MASTER TRANSFERS TO SLAVE
SLAVE TRANSFERS TO MASTER
A = ACK; A = 0: SUCCESSFUL, A = 1: UNSUCCESSFUL
S = START CONDITION
P = STOP CONDITION
Figure 4. Serial-Interface Data Structure
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX9476EUG | 功能描述:时钟发生器及支持产品 35.328MHz Clock Synthesizer RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX9476EUG-T | 功能描述:时钟发生器及支持产品 35.328MHz Clock Synthesizer RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MAX9480EUP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX9481EUP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX9482EUI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
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