参数资料
型号: MAX9471ETP+T
厂商: Maxim Integrated Products
文件页数: 3/13页
文件大小: 0K
描述: IC MULTI-PURPOSE CLK GEN 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 时钟发生器
PLL:
输入: LVCMOS,晶体
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 2:4
差分 - 输入:输出: 无/无
频率 - 最大: 200MHz
除法器/乘法器: 无/无
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX9471/MAX9472
Multiple-Output Clock Generators with
Dual PLLs and OTP
______________________________________________________________________________________
11
Applications Information
Crystal Selection
When using a crystal with the MAX9471/MAX9472s’
internal oscillator, connect the crystal to X1 and X2.
Choose an AT-cut crystal that oscillates on its funda-
mental mode with ±30ppm and loading capacitance
less than 14pF. To achieve a wide VCXO tuning range,
select a crystal with motional capacitance greater than
7fF and connect 6pF or less shunt capacitors at X1 and
X2 to ground. When the VCXO is used as an oscillator,
select both shunt capacitors to be approximately 13pF.
The optimal shunt capacitors for achieving minimum
frequency offset can be determined experimentally.
Board Layout Considerations and
Bypassing
The MAX9471/MAX9472s’ oscillator frequencies make
proper layout important to ensure stability. For best per-
formance, place components as close as possible to
the device.
Digital or AC transient signals on GND can create noise
at the clock output. Return GND to the highest quality
ground available. Bypass each VDD and VDDA with a
0.1F capacitor, placed as close as possible to the
device. Careful PC board ground layout minimizes
crosstalk between the outputs and digital inputs.
Chip Information
PROCESS: CMOS
14
13
12
11
10
9
8
1
2
3
4
5
6
7
X2
VDD
GND
VDD
FS0
FS1
X1
TOP VIEW
GND
CLK3
CLK2
CLK1
GND
TUNE
MAX9472
TSSOP
PD
+
Pin Configurations (continued)
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