参数资料
型号: MAX9761EUI+T
厂商: Maxim Integrated Products
文件页数: 8/31页
文件大小: 0K
描述: IC AMP AUDIO PWR 3W STER 28TSSOP
标准包装: 2,500
类型: AB 类
输出类型: 2-通道(立体声)带立体声耳机
在某负载时最大输出功率 x 通道数量: 3W x 2 @ 3 欧姆; 200mW x 2 @ 16 欧姆
电源电压: 4.5 V ~ 5.5 V
特点: 消除爆音,输入多路复用器,静音,关机,热保护,
安装类型: 表面贴装
供应商设备封装: 28-TSSOP 裸露焊盘
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
MAX9760–MAX9763
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
16
______________________________________________________________________________________
MAX9762. The master terminates transmission by issu-
ing the STOP condition, this frees the bus. If a REPEAT-
ED START condition is generated instead of a STOP
condition, the bus remains active.
Early STOP Conditions
The MAX9760/MAX9762 recognize a STOP condition at
any point during the transmission except if a STOP con-
dition occurs in the same high pulse as a START condi-
tion (Figure 5). This condition is not a legal I2C format,
at least one clock pulse must separate any START and
STOP conditions.
REPEATED START Conditions
A REPEATED START (Sr) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Sr may also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX9760/
MAX9762 serial interface supports continuous write
operations with or without an Sr condition separating
them. Continuous read operations require Sr conditions
because of the change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9760/MAX9762 generate an ACK
when receiving an address or data by pulling SDA low
during the night clock period. When transmitting data,
the MAX9760/MAX9762 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
Slave Address
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9760/
MAX9762 wait for a START condition followed by its
slave address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the master
is writing to or reading from the MAX9760/MAX9762
(R/W = 0 selects the write condition, R/W = 1 selects
the read condition). After receiving the proper address,
the MAX9760/MAX9762 issue an ACK by pulling SDA
low for one clock cycle.
The MAX9760/MAX9762 have a factory-/user-pro-
grammed address. Address bits A6–A2 are preset,
while A0 and A1 is set by ADD. Connect ADD to either
VDD, GND, SCL, or SDA to change the last 2 bits of the
slave address (Table 2).
Write Data Format
There are three registers that configure the
MAX9760/MAX9762: the MUTE register, SHDN register,
and control register. In write data mode (R/W = 0), the
register address and data byte follow the device
address (Figure 7).
MUTE Register
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel, bit 4
(MUTER) controls the right channel. A logic high mutes
the respective channel, a logic low brings the channel
out of mute.
SHDN Register
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic high
in bit 0 of the SHDN register shuts down the device; a
logic low turns on the device. A logic high is required in
bits 2 to 7 to reset all registers to their default settings.
SCL
SDA
STOP
START
SCL
SDA
ILLEGAL
STOP
START
LEGAL STOP CONDITION
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
S
A6A5A4A3A2A1A0
R/W
Figure 6. Slave Address Byte Definition
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