参数资料
型号: MAX9853ETM+
厂商: Maxim Integrated Products
文件页数: 43/71页
文件大小: 0K
描述: IC CODEC AUDIO STEREO 48TQFN
标准包装: 43
类型: 立体声音频
数据接口: 串行
分辨率(位): 18 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 81.5 / 88
动态范围,标准 ADC / DAC (db): 82 / 87.5
电压 - 电源,模拟: 2.6 V ~ 3.3 V
电压 - 电源,数字: 1.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(7x7)
包装: 管件
MAX9851/MAX9853
Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
48
______________________________________________________________________________________
Master Mode (S1MAS/S2MAS)
1 = Master mode (LRCLK and BCLK timing signals
generated internally; LRCLK and BCLK configured as
outputs).
0 = Slave mode (LRCLK and BCLK accepted from
external source; LRCLK and BCLK configured as
inputs).
Slave mode timing signals may operate asynchronous
to either the MCLK or the other audio interface source
in DAC-only stereo audio modes. An interface with the
ADC output enabled must operate in master mode,
unless operating synchronously in voice mode.
LRCLK Invert (S1WCI/S2WCI)
1 = Right-channel data is transmitted while LRCLK is
low.
0 = Left-channel data is transmitted while LRCLK is
low.
Set S1WCI/S2WCI = 0 to conform to the I2S standard.
S1WCI/S2WCI have no effect in voice mode.
BCLK Invert (S1BCI/S2BCI)
1 = Digital audio bits are transferred on the falling edge
of BCLK.
0 = Digital audio bits are transferred on the rising edge
of BCLK.
Set S1BCI/S2BCI = 0 to conform to the I2S standard.
Data Delay (S1DLY/S2DLY)
1 = Digital audio MSB on SDIN and SDOUT is trans-
ferred on the 2nd BCLK edge following an LRCLK edge.
0 = Digital audio MSB on SDIN and SDOUT is trans-
ferred on the 1st BCLK edge following an LRCLK edge.
Set S1DLY/S2DLY = 1 to conform to the I2S standard.
S1DLY/S2DLY have no effect in voice mode.
Word Size (S1WS/S2WS)
1 = 18-bit digital audio data.
0 = 16-bit digital audio data.
When operating in master mode, the number of BLCK
cycles per sample corresponds to the word size select-
ed by S1WS/S2WS. S1WS/S2WS have no effect in
voice mode.
MCLK Frequency Mode (MHz)
1 = 26MHz MCLK.
0 = 13MHz MCLK.
A 26MHz clock allows for synchronous 16kHz voice
mode. All other modes of operation can operate from
either MCLK frequency.
ADC DC-Blocking Filter Enable (ADCDC)
1 = ADC DC block enabled.
0 = ADC DC block disabled.
DC-blocking consists of a highpass filter with a cutoff
frequency of fS / 1608. This filter is available in all modes
of operation including voice modes. The ADC DC-
blocking filter can be overloaded with low-frequency
signals with DC offset greater than ±0.125V (one-eighth
full scale).
ADC Bandpass Filter Enable (ABPE)
1 = ADC bandpass filter enabled.
0 = ADC bandpass filter disabled.
ABPE = 1 enables the ADC highpass filter in combina-
tion with the ADC lowpass filter to create a bandpass
filter. The ADC voiceband filters only operate on the left
output channel data of voiceband, the ADC, and when
operating in voice mode.
DAC Bandpass Filter Enable (DBPE)
1 = DAC bandpass filter enabled.
0 = DAC bandpass filter disabled.
DBPE = 1 enables the DAC highpass filter in combina-
tion with the DAC lowpass filter to create a bandpass
filter. The DAC filters only operate on the S1 left input or
mono S1 L+R input signal data.
Left and Right DAC Highpass Filter Mode
(DHPL/DHPR)
00 = No filtering.
01 = 55Hz to 91Hz cutoff frequency.
10 = 171Hz to 279Hz cutoff frequency.
11 = 327Hz to 533Hz cutoff frequency.
When both the ADC and DAC are enabled, the exact
cutoff frequency of each setting depends on the sam-
ple rate in use. In DAC-only mode, the exact cutoff fre-
quency will be the high end of the range above.
Table 14. Digital Filter
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x07
MHZ
ADCDC
ABPE
DBPE
DHPL
DHPR
Digital Filter Register (0x07)
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MAX9851ETM+ IC CODEC AUDIO STEREO 48TQFN-EP
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