参数资料
型号: MAXQ7666BATM+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 微控制器/微处理器
英文描述: RISC MICROCONTROLLER, QCC48
封装: 7 X 7 MM, ROHS COMPLAINT, TQFN-48
文件页数: 11/49页
文件大小: 2130K
代理商: MAXQ7666BATM+
MAXQ7666
16-Bit, RISC, Microcontroller-Based,
Smart Data-Acquisition System
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19
Pin Description (continued)
PIN
NAME
FUNCTION
32
P0.0/TDO
Port 0 Data 0/JTAG Serial Test Data Output. P0.0 is a general-purpose digital I/O with
interrupt/wake-up capability. TDO is the JTAG serial test, data output. Refer to the
MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10.
33
P0.1/TMS
Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wake-
up capability. TMS is the JTAG test mode select input. Refer to the MAXQ7665/MAXQ7666
User’s Guide sections 8 and 10.
34
P0.2/TDI
Port 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with
interrupt/wake-up capability. TDI is the JTAG serial test, data input. Refer to the
MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10.
35
P0.3/TCK
Port 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with
interrupt/wake-up capability. TCK is the JTAG serial test, clock input. Refer to the
MAXQ7665/MAXQ7666 User’s Guide sections 8 and 10.
36
P0.4/ADCCNV
Port 0 Data 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wake-
up capability. ADCCNV is firmware configurable for a rising or falling edge start/convert to trigger
ADC conversions. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 3 and 8.
37
P0.5/DACLOAD
Port 0 Data 5/DAC Data Register Load/Update Input. P0.5 is a general-purpose digital I/O with
interrupt/wake-up capability. DACLOAD is firmware configurable for a rising or falling edge to
update the DACOUT register. Refer to the MAXQ7665/MAXQ7666 User’s Guide sections 3 and 8.
38
REGEN
Active-Low Linear Regulator Enable Input. Connect
REGEN to GNDIO to enable the linear
regulator. Connect
REGEN to DVDDIO to disable the linear regulator.
40
DVDD
Digital Supply Voltage. DVDD supplies the internal digital core and flash memory. DVDD is internally
connected to the output of the internal 3.3V linear regulator. Disable the internal regulator to connect
DVDD to an external supply. When using the on-chip linear regulator, bypass DVDD to DGND with a
4.7F ±20% capacitor with a maximum ESR of 0.5
Ω. In addition, bypass DVDD with a 0.1F
capacitor. Place both bypass capacitors as close as possible to the device.
41
RESET
Reset Input and Output. Active-low open-drain input/output with internal 305k
Ω (typ) pullup to
DVDD. Drive low to reset the C. RESET is low during power-up reset and during DVDD brownout
conditions.
42
XOUT
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal
operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not
driven when using the internal RC oscillator.
43
XIN
High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for
normal operation, or drive XIN with an external clock source. XIN is not driven when using the
internal RC oscillator.
44
AVDD
Analog Supply Voltage Input. Connect AVDD to a +5V supply. Bypass AVDD to AGND with a
0.1F capacitor placed as close as possible to the device.
45
AIN15
Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14.
46
AIN14
Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15.
47
AIN13
Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12.
48
AIN12
Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13.
EP
Exposed Pad. EP is internally connected to AGND. Connect EP to AGND externally.
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