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MAXQ7666
16-Bit, RISC, Microcontroller-Based,
Smart Data-Acquisition System
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25
set to their default state. The VDBR bits retain their
value if DVDD falls below the BOR threshold but
remains above the POR threshold.
The following scenarios apply once DVDD enters BOR:
If DVDD remains below the BOR threshold, the
RESET pin remains low, and the C remains in the
reset state.
If DVDD stops falling before reaching the POR
threshold, then begins rising above the BOR thresh-
old, the
RESET pin is released and the C jumps to
the reset vector (8000h in the utility ROM). This is
similar to the DVDD power-up case described in the
previous scenario, except there is no power-up
counter delay and some of the register bits are set
to BOR values rather than POR values. See Tables 3
and 5 for the reset behavior of specific bits. In par-
ticular, the retained VDBR setting, if higher than the
default value of 00b, allows a potentially more robust
brownout recovery closer to or above the minimum
flash operating level of +3.0V.
If DVDD falls below the 1.2V POR threshold, all regis-
ter bits are reset, and any DVDD recovery from that
point is identical to the power-up case described
above. See Tables 3 and 5 for the reset behavior of
specific bits.
Refer to the
MAXQ7665/MAXQ7666 User’s Guide for
detailed programming information, and a more thor-
ough description of POR and brownout behavior.
Internal 3.3V Linear Regulator
An internal +3.3V/50mA linear regulator provides alter-
nate supply to the MAXQ7666 core logic if an external
supply is not used. Connect
REGEN to GNDIO to
enable the linear regulator. When using the linear regu-
lator, ensure the DVDDIO supply can support both the
I/O and digital supply current requirements. Connect
REGEN to DVDDIO when using a +3.3V external sup-
ply. Apply DVDDIO before DVDD when using external
supply for DVDD.
System Clock Generator
The MAXQ7666 oscillator module is the master clock
generator that supplies the system clock for the C
core and all of the peripheral modules using either a
crystal oscillator or an internal RC oscillator. The crystal
oscillator operates with an 8MHz crystal. Use the RC
oscillator in applications that do not require precise tim-
ing. The MAXQ7666 executes most instructions in a
single SYSCLK period. The oscillator module contains
all of the primary clock-generation circuitry. Figure 6
shows a block diagram of the system clock module.
The MAXQ7666 supports many features for generating
a master clock signal timing source:
Internal, fast-starting, 7.6MHz RC oscillator elimi-
nates external crystal
Internal high-frequency oscillator that can drive an
external 8MHz crystal
External high-frequency clock input (8MHz)
Selectable internal capacitors for high-frequency
crystal oscillator
Power-up timer
Fail-safe modes
Watchdog Timer
The primary function of the watchdog timer is to watch
for stalled or stuck software. The watchdog timer per-
forms a controlled system restart when the P fails to
write to the watchdog timer register before a selectable
timeout interval expires. In some designs, the watchdog
timer is also used to implement a real-time operating
system (RTOS) in the C. When used to implement an
RTOS, a watchdog timer typically has four objectives:
1) To detect if a system is operating normally
2) To detect an infinite loop in any of the tasks
3) To detect an arbitration deadlock involving two or
more tasks
4) To detect if some lower priority tasks are not running
because of higher priority tasks
CD0
SYSCLK
MUX
HFRCCLK
CLOCK
DIVIDE
HF
XTAL
OSC
RC
OSC
XIN
XOUT
XT
EXTHF
RCE
HFE
Figure 6. Crystal and RC Oscillator Block Diagram