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参数资料
| 型号： | MB88R157PNF-G-JNE1 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 134 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 5.05 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8 |
| 文件页数： | 22/24页 |
| 文件大小： | 724K |
| 代理商： | MB88R157PNF-G-JNE1 |
MB88R157
DS04-29132-3E
7
■ OPERATION SETTING
Frequency setting
Output frequency can be set by writing the internal memory to each divider parameter in the PLL block.
Internal oscillation frequency and output frequency can be calculated following expressions :
Internal oscillation frequency (fvco*)
= Input frequency (fin) × (M+1) / (N+1)
* : Please set the fvco range from 20 MHz to 134 MHz.
Output frequency (fOUT*)
= Input frequency (fin) × (M+1) / ( (N+1) × K)
* : Please set the fOUT range from 1 MHz to 134 MHz.
(Setting example)
fin
= 27 MHz, fOUT = 60 MHz
M divider parameter : 1999 (
= 7CFH) , N divider parameter : 899 ( = 383H) , K divider parameter : 1 ( = 01H)
27
× (1999+1) / ( (899+1) × 1) = 60 [MHz] (fvco = 27 × (1999+1) / (899+1) = 60 [MHz])
Note: Recommended value of each divider parameter is different at PLL mode and normal mode. Please refer
and confirm the recommended value by our support tool. Contact the sales representatives for details on
the support tools.
Modulation frequency setting
Modulation frequency can be set by writing the internal memory to L divider parameter.
The average of modulation frequency can be calculated following expressions :
Note: Please refer and confirm the recommended value by our support tool. Contact the sales representatives for
details on the support tools.
Modulation rate setting
Modulation rate can be selectable from no modulation,
±0.25%, ±0.50%, ±0.75%, ±1.00%, ±1.25%, ±1.50%,
±1.75%.
Input frequency
266
× (L+1)
(L
= 1, 2, 3, 4, 5, 6, 7)
bit44
bit43
bit42
Modulation rate setting
0
No modulation
001
±0.25%
010
±0.50%
011
±0.75%
100
±1.00%
101
±1.25%
110
±1.50%
111
±1.75%
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