参数资料
型号: MB88R157PNF-G-JNE1
厂商: FUJITSU LTD
元件分类: 时钟产生/分配
英文描述: 134 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 5.05 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8
文件页数: 7/24页
文件大小: 724K
代理商: MB88R157PNF-G-JNE1
MB88R157
DS04-29132-3E
15
AC characteristics (1)
(Ta
= 20 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V)
* : The duty cycle value (tDCR) of the source clock output depends on the duty cycle of input clock tDCI. Either case
of A or B will be guaranteed.
A. Resonator
: Oscillating with the resonator connected with XIN, XOUT
B. External clock input : The input level is Full - swing (VSS - VDD).
Parameter
Sym-
bol
Pin
name
Conditions
Value
Unit
Min
Typ
Max
Crystal oscillation
frequency
fx
XIN,
XOUT
Fundamental oscillation
10
40
MHz
Input frequency
fin
XIN
10
40
MHz
Internal oscillation
frequency
fVCO
20
134
MHz
Output frequency
fOUT
OUT
Operation in PLL mode
and at non modulation
1
134
MHz
Operation at modulation
16
134
Output slewing rate
SR
0.4 V to 2.4 V
load capacitance 15 pF
Driving ability small:
at 1 MHz to 60 MHz out-
put
Driving ability large:
at 60 MHz to 134 MHz
output
0.3
V/ns
Output impedance
ZO
Driving ability small
75
Ω
Driving ability large
38
Output clock duty
cycle
tDCC
VCO clock output
45
55
%
tDCR
At reference clock
output
tDCI
10*
tDCI
+10*
Modulation
frequency (number
of clocks par one
modulation)
fMOD
(nMOD)
fin/ (224
×
(L+1) )
(224
× (L+1) )
fin/ (266
×
(L+1) )
(266
× (L+1) )
fin/ (308
×
(L+1) )
(308
× (L+1) )
kHz
(clks)
Power supply time
tR
VDD
0.2 V to 3.0 V
0.05
20
ms
Lock-up time
tLK
OUT
270/fin+5
270/fin+10
ms
Cycle-cycle jitter
tJC
No load
capacitance,
Ta
= + 25 °C
VDD
= 3.3 V
fOUT
2 MHz
100
ps-
rms
fOUT<
2 MHz
150
Output stop time
from OE exit.
tOD
ta
= 1 / fOUT
2
× ta
ns
Output start time
after OE entry
tOE
ta
= 1 / fOUT
2
× ta
ns
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