参数资料
型号: MB88R157PNF-G-JNE1
厂商: FUJITSU LTD
元件分类: 时钟产生/分配
英文描述: 134 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 5.05 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8
文件页数: 23/24页
文件大小: 724K
代理商: MB88R157PNF-G-JNE1
MB88R157
8
DS04-29132-3E
Charge Pump setting, VCO gain setting
Note: Please refer and confirm the recommended value by our support tool. Contact the sales representatives for
details on the support tools.
OUT pin setting
OUT pin situation can be selected at OE pin “L” input.
Note : Internal oscillation circuit has been operating when OE pin is input “L”.
Output drive ability setting
Output drive ability of OUT pin can be selected.
Source clock dividing setting
Source clock to K divider can be selected.
When “input frequency” is selected, source clock or its divided clock can be output. But modulation setting is
not enable.
Note: When “input frequency ” is selected, internal oscillation circuit has been operating. About M and N divider
parameter setting, please refer and confirm the recommended value by our support tool. Contact the sales
representatives for details on the support tools.
PLL mode setting
It can be selected normal mode and PLL mode by bit48 setting in the memory map. PLL mode is good jitter
specification at non modulation. When the mode is selected, it becomes non modulation setting, the resistance
and capacitance value of the loop filter is changed, so oscillation specification is change.
Note: When PLL mode is selected, recommended value of M, N, K divider is changed. Please refer and confirm
the recommended value by our support tool. Contact the sales representatives for details on the support tools.
bit45
OUT pin situation
0
“L” output
1
“Hi-Z” output
bit46
OUT pin drive ability
0
Small (IOL
= 3 mA)
1
Large (IOL
= 7 mA)
bit47
Source clock to K divider
0
VCO output clock
1
Input clock (Source clock)
bit48
Operation mode
0
SSCG mode
1
PLL mode
相关PDF资料
PDF描述
MB88R157PNF-G-JN-EFE1 134 MHz, OTHER CLOCK GENERATOR, PDSO8
MB88R157PNF-G-JN-ERE1 134 MHz, OTHER CLOCK GENERATOR, PDSO8
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