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参数资料
| 型号： | MB90F498GPMC |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 55/96页 |
| 文件大小： | 2317K |
| 代理商： | MB90F498GPMC |
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MB90495G Series
DS07-13713-6E
59
13. ROM Correction Function
In the case that the address of the instruction after the one that a program is currently processing matches the
address configured in the detection address configuration register, the program forces the next instruction to be
processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be
conducted using INT9 interrupts, programs can be repaired using batch processing.
Overview of the ROM Correction Function
The address of the instruction after the one that a program is currently processing is always stored in an
address latch via the internal data bus. ROM correction constantly compares the address stored in the address
latch with the one configured in the detection address configuration register. If the two compared addresses
match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing
program.
There are two detection address configuration registers : PADR0 and PADR1. Each register provides an
interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of
interrupts when the address stored in the address latch matches the one configured in the detection address
configuration register.
ROM Correction Block Diagram
Address latch
Stores value of address output to internal data bus.
Address detection control register (PACSR)
Set this register to enable/prohibit interrupt output when an address match is detected.
Detection address configuration register (PADR0, PADR1)
Configure an address with which to compare the address latch value.
AD1E
AD0E
PADR1 (24-bit)
PADR0 (24-bit)
PACSR
Inter
nal
data
b
us
Address latch
Detection address configuration register 0
Detection address configuration register 1
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Address detection control register (PACSR)
Compar
ator
INT9 instruction
(INT9 interrupt generation)
Reserved : Make sure this is always set to “01”
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| MB90F543GPF-GE1 | 功能描述:IC MCU 16BIT 制造商:cypress semiconductor corp 系列:F2MC-16LX MB90540G 包装:托盘 零件状态:在售 核心处理器:F2MC-16LX 核心尺寸:16-位 速度:16MHz 连接性:CAN，EBI/EMI，SCI，串行输入/输出，UART/USART 外设:POR，WDT I/O 数:81 程序存储容量:128KB（128K x 8） 程序存储器类型:闪存 EEPROM 容量:- RAM 容量:6K x 8 电压 - 电源（Vcc/Vdd）:4.5 V ~ 5.5 V 数据转换器:A/D 8x8/10b 振荡器类型:外部 工作温度:-40°C ~ 105°C（TA） 封装/外壳:100-BQFP 供应商器件封装:100-PQFP（20x14） 标准包装:66 |
| MB90F543GPFR-GE1 | 制造商:FUJITSU 功能描述: |
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