MB90800 Series
DS07-13733-6E
79
(8) I2C timing
(AVCC
= VCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock timing”.
*2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “
Note of SDA and SCL set-up time”.
Parameter
Symbol
Conditions
Standard-
mode
Unit
Min
Max
SCL clock frequency
fSCL
When power supply voltage of external
pull-up resistor is 5.0 V
R
= 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
R
= 1.0 kΩ, C = 50 pF*2
0100
kHz
Hold time (repeated) START condition
SDA
↓ → SCL ↓
tHDSTA
4.0
μs
“L” width of the SCL clock
tLOW
4.7
μs
“H” width of the SCL clock
tHIGH
4.0
μs
Set-up time for a repeated START condition
SCL
↑ → SDA ↓
tSUSTA
4.7
μs
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
0
3.45
*3
μs
Data set-up time
SDA
↓ ↑ → SCL ↑
tSUDAT
When power supply voltage of external
pull-up resistor is 5.0 V
fCP*1
≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
fCP*1
≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
250
*4
ns
When power supply voltage of external
pull-up resistor is 5.0 V
fCP*1
> 20 MHz, R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
fCP*1
> 20 MHz, R = 1.0 kΩ, C = 50 pF*2
200
*4
ns
Set-up time for STOP condition
SCL
↑ → SDA ↑
tSUSTO
When power supply voltage of external
pull-up resistor is 5.0 V
R
= 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
R
= 1.0 kΩ, C = 50 pF*2
4.0
μs
Bus free time between a STOP and START
condition
tBUS
4.7
μs