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参数资料
| 型号： | MB91F267APMC-GE1 |
| 厂商： | Fujitsu Semiconductor America Inc |
| 文件页数： | 37/53页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 128KB FLASH 64LQFP |
| 标准包装： | 1 |
| 系列： | FR MB91265A |
| 核心处理器： | FR60Lite RISC |
| 芯体尺寸： | 32-位 |
| 速度： | 33MHz |
| 连通性： | UART/USART |
| 外围设备： | DMA，WDT |
| 输入/输出数： | 49 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 数据转换器： | A/D 11x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 64-LQFP |
| 包装： | 托盘 |
| 其它名称： | 865-1092 |
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45
8183F–AVR–06/12
ATtiny24A/44A/84A
the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after
each interrupt.
Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. See the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the
Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
ten to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above. See “Timed Sequences for Changing the Configuration of the Watchdog
In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Regis-
ter” on page 44 for description of WDRF. This means that WDE is always set when WDRF is set.
To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure
described above. This feature ensures multiple resets during conditions causing failure, and a
safe start-up after the failure.
Note:
If the watchdog timer is not going to be used in the application, it is important to go through a
watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally
enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which
in turn will lead to a new watchdog reset. To avoid this situation, the application software should
always clear the WDRF flag and the WDE control bit in the initialization routine.
Table 8-2.
Watchdog Timer Configuration
WDE
WDIE
Watchdog Timer State
Action on Time-out
0
Stopped
None
0
1
Running
Interrupt
1
0
Running
Reset
1
Running
Interrupt
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB91F267APMC-GS | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
| MB91F267APMC-GSE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
| MB91F267N | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontroller |
| MB91F267NA | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
| MB91F267NAPMC-G | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers |
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