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参数资料
| 型号： | MB91F267NAPMC-GSE1 |
| 厂商： | Fujitsu Semiconductor America Inc |
| 文件页数： | 10/53页 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 128KB FLASH 64LQFP |
| 标准包装： | 1 |
| 系列： | FR MB91265A |
| 核心处理器： | FR60Lite RISC |
| 芯体尺寸： | 32-位 |
| 速度： | 33MHz |
| 连通性： | CAN，UART/USART |
| 外围设备： | DMA，WDT |
| 输入/输出数： | 49 |
| 程序存储器容量： | 128KB（128K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 数据转换器： | A/D 11x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 64-LQFP |
| 包装： | 托盘 |
| 配用： | 865-1102-ND - BOARD EVAL RS232 100QFP |
| 其它名称： | 865-1091 |
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20
8183F–AVR–06/12
ATtiny24A/44A/84A
be used. If a reset occurs while a write operation is in progress, the write operation will be com-
pleted provided that the power supply voltage is sufficient.
5.4
I/O Memory
The I/O space definition of the ATtiny24A/44A/84A is shown in “Register Summary” on page
All ATtiny24A/44A/84A I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. See the instruction
set section for more details. When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
5.4.1
General Purpose I/O Registers
The ATtiny24A/44A/84A contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and
status flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
5.5
Register Description
5.5.1
EEARH – EEPROM Address Register
Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 0 – EEAR8: EEPROM Address
This is the most significant EEPROM address bit of ATtiny84A. In devices with less EEPROM,
i.e. ATtiny24A/ATtiny44A, this bit is reserved and will always read zero. The initial value of the
EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written
before the EEPROM is accessed.
Bit
765
432
10
–––
–
EEAR8
EEARH
Read/Write
RR
RRR
RR
R/W
Initial Value
0
X/0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB91F267NPMC-G | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontroller |
| MB91F267NPMC-GE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontroller |
| MB91F267NPMC-GS | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontroller |
| MB91F267NPMC-GSE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontroller |
| MB91F267NPMCR-GE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT FR 128K FLASH 64LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, FR, 128K FLASH, 64LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, FR, 128K FLASH, 64LQFP, Controller Family/Series:FR60, Core Size:32b 制造商:FUJITSU 功能描述:IC, 32BIT MCU, FR60, 33MHZ, LQFP-64, Controller Family/Series:FR60, Core Size:32bit, No. of I/O's:48, Supply Voltage Min:4V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:64, Program Memory Size:128KB, MSL:- , RoHS Compliant: Yes |
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