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参数资料
| 型号： | MB91F346BPFT-GE1 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 12 X 12 MM, 1.20 MM HEIGHT, 0.40 MM PITCH, PLASTIC, TQFP-100 |
| 文件页数： | 55/72页 |
| 文件大小： | 657K |
| 代理商： | MB91F346BPFT-GE1 |
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MB91345 Series
59
(7) I2C timing
At master mode operating
(VCC
= AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 40 °C to + 85 °C)
*1 : M
= Resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies
a requirement of “tSUDAT
≥ 250 ns”.
When a device does not extend the “L” period of the SCL signal, the next data must be outputted to the SDA
line within 1250 ns (maximum SDA/SCL rise time
+ tSUDAT) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
Parameter
Symbol
Pin
name
Conditions
Typical mode
High-speed
mode*3
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
SDA0
to
SDA10,
SCL0
to
SCL10
R
= 1 k
C
= 50 pF*4
0
100
0
400
kHz
“L” period of SCL
clock
tLOW
4.7
1.3
s
“H” period of SCL
clock
tHIGH
4.0
0.6
s
SCL
↓ → SDA output
delay time
tDLDAT
5
× M*1
5
× M*1 ns
Bus free time
between [STOP
condition] and
[START condition]
tBUS
4.7
1.3
s
SDA data input hold
time (vs. SCL
↓)
tHDDAT
2
× M*1
2
× M*1
s
SDA data input setup
time (vs. SCL
↑)
tSUDAT
250
100*2
ns
Setup time of
[repeat START
condition]
SCL
↑ → SDA↓
tSUSTA
4.7
0.6
s
Hold time of [repeat
START condition]
SDA
↓ → SCL↓
tHDSTA
4.0
0.6
s
After that, the
first clock pulse
is generated.
Setup time of [STOP
condition]
SCL
↑ → SDA↑
tSUSTO
4.0
0.6
s
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相关代理商/技术参数 |
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