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| 型号： | MB95F262KPF-G-SNE2 |
| 厂商： | Fujitsu Semiconductor America Inc |
| 文件页数： | 70/87页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 8KB FLASH 20SOP |
| 标准包装： | 1,400 |
| 系列： | 8FX MB95260H |
| 核心处理器： | F²MC-8FX |
| 芯体尺寸： | 8-位 |
| 速度： | 16MHz |
| 连通性： | LIN，SIO，UART/USART |
| 外围设备： | LVD，POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 240 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 数据转换器： | A/D 6x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 包装： | 托盘 |
| 其它名称： | 865-1209 |
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2011 Microchip Technology Inc.
DS70118J-page 77
dsPIC30F2010
13.3
Position Measurement Mode
There are two Measurement modes which are sup-
ported and are termed x2 and x4. These modes are
selected by the QEIM<2:0> mode select bits located in
SFR QEICON<10:8>.
When control bits QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A signal causes the position counter to be incre-
mented or decremented. The Phase B signal is still
utilized for the determination of the counter direction,
just as in the x4 mode.
Within the x2 Measurement mode, there are two
variations of how the position counter is reset:
1.
Position counter reset by detection of index
pulse, QEIM<2:0> = 100.
2.
Position counter reset by match with MAXCNT,
QEIM<2:0> = 101.
When control bits QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input sig-
nals. Every edge of both signals causes the position
counter to increment or decrement.
Within the x4 Measurement mode, there are two
variations of how the position counter is reset:
1.
Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
2.
Position counter reset by match with MAXCNT,
QEIM<2:0> = 111.
The x4 Measurement mode provides for finer resolu-
tion data (more position counts) for determining motor
position.
13.4
Programmable Digital Noise
Filters
The digital noise filter section is responsible for
rejecting noise on the incoming quadrature signals.
Schmitt Trigger inputs and a three-clock cycle delay fil-
ter combine to reject low level noise and large, short
duration noise spikes that typically occur in noise prone
applications, such as a motor system.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.
For the QEA, QEB and INDX pins, the clock divide fre-
quency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>) and are derived from
the base instruction cycle TCY.
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR and BOR.
13.5
Alternate 16-bit Timer/Counter
When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
as a simple 16-bit timer/counter. The setup and control
of the auxiliary timer is accomplished through the QEI-
CON SFR register. This timer functions identically to
Timer1. The QEA pin is used as the timer clock input.
When configured as a timer, the POSCNT register
serves as the Timer Count Register and the MAXCNT
register serves as the Period Register. When a timer/
period register match occur, the QEI interrupt flag will
be asserted.
The only exception between the general purpose tim-
ers and this timer is the added feature of external Up/
Down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
The UPDN control/status bit (QEICON<11>) can be
used to select the count direction state of the Timer reg-
ister. When UPDN = 1, the timer will count up. When
UPDN = 0, the timer will count down.
In addition, control bit UPDN_SRC (QEICON<0>)
determines whether the timer count direction state is
based on the logic state, written into the UPDN control/
status bit (QEICON<11>), or the QEB pin state. When
UPDN_SRC = 1, the timer count direction is controlled
from the QEB pin. Likewise, when UPDN_SRC = 0, the
timer count direction is controlled by the UPDN bit.
13.6
QEI Module Operation During CPU
Sleep Mode
13.6.1
QEI OPERATION DURING CPU
SLEEP MODE
The QEI module will be halted during the CPU Sleep
mode.
13.6.2
TIMER OPERATION DURING CPU
SLEEP MODE
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
Note:
Changing the Operational mode (i.e., from
QEI to Timer or vice versa), will not affect
the
Timer/Position
Count
Register
contents.
Note:
This Timer does not support the External
Asynchronous Counter mode of operation.
If using an external clock source, the clock
will automatically be synchronized to the
internal instruction cycle.
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