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| 型号： | MB95F262KPF-G-SNE2 |
| 厂商： | Fujitsu Semiconductor America Inc |
| 文件页数： | 82/87页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 8KB FLASH 20SOP |
| 标准包装： | 1,400 |
| 系列： | 8FX MB95260H |
| 核心处理器： | F²MC-8FX |
| 芯体尺寸： | 8-位 |
| 速度： | 16MHz |
| 连通性： | LIN，SIO，UART/USART |
| 外围设备： | LVD，POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 240 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 数据转换器： | A/D 6x8/10b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 包装： | 托盘 |
| 其它名称： | 865-1209 |
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dsPIC30F2010
DS70118J-page 88
2011 Microchip Technology Inc.
14.11 PWM Output and Polarity Control
There are three device Configuration bits associated
with the PWM module that provide PWM output pin
control:
HPOL Configuration bit
LPOL Configuration bit
PWMPIN Configuration bit
These three bits in the FBORPOR Configuration regis-
ters”) work in conjunction with the three PWM enable
bits (PWMEN<3:1>) located in the PWMCON1 SFR.
The Configuration bits and PWM enable bits ensure
that the PWM pins are in the correct states after a
device Reset occurs. The PWMPIN configuration fuse
allows the PWM module outputs to be optionally
enabled on a device Reset. If PWMPIN = 0, the PWM
outputs will be driven to their inactive states at Reset. If
PWMPIN = 1 (default), the PWM outputs will be tri-
stated. The HPOL bit specifies the polarity for the
PWMxH outputs, whereas the LPOL bit specifies the
polarity for the PWMxL outputs.
14.11.1
OUTPUT PIN CONTROL
The PENxH and PENxL control bits in the PWMCON1
SFR enable each high PWM output pin and each low
PWM output pin, respectively. If a particular PWM out-
put pin not enabled, it is treated as a general purpose
I/O pin.
14.12 PWM FLTA Pin
There is one Fault input pin (FLTA) associated with the
PWM module. When asserted, this pin can optionally
drive each of the PWM I/O pins to a defined state.
14.12.1
FAULT PIN ENABLE BITS
The FLTACON SFR has 4 control bits that determine
whether a particular pair of PWM I/O pins is to be con-
trolled by the FLTA input pin. To enable a specific PWM
I/O pin pair for FLTA overrides, the corresponding bit
should be set in the FLTACON register.
If all enable bits are cleared in the FLTACON register,
then the FLTA input pin has no effect on the PWM
module and the pin may be used as a general purpose
interrupt or I/O pin.
14.12.2
FAULT STATES
The FLTACON special function register has eight bits
that determine the state of each PWM I/O pin when it is
overridden by a FLTA input. When these bits are
cleared, the PWM I/O pin is driven to the inactive state.
If the bit is set, the PWM I/O pin will be driven to the
active state. The active and inactive states are refer-
enced to the polarity defined for each PWM I/O pin
(HPOL and LPOL polarity control bits).
14.12.3
FAULT INPUT MODES
The FLTA input pin has two modes of operation:
Latched Mode: When the FLTA pin is driven low,
the PWM outputs will go to the states defined in
the FLTACON register. The PWM outputs will
remain in this state until the FLTA pin is driven
high and the corresponding interrupt flag has
been cleared in software. When both of these
actions have occurred, the PWM outputs will
return to normal operation at the beginning of the
next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the FLTA condition
ends, the PWM module will wait until the FLTA pin
is no longer asserted to restore the outputs.
Cycle-by-Cycle Mode: When the FLTA input pin
is driven low, the PWM outputs remain in the
defined FLTA states for as long as the FLTA pin is
held low. After the FLTA pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
The Operating mode for the FLTA input pin is selected
using the FLTAM control bit in the FLTACON Special
Function Register.
The FLTA pin can be controlled manually in software.
14.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four duty cycle registers and the time base
period register, PTPER, at a given time. In some appli-
cations, it is important that all buffer registers be written
before the new duty cycle and period values are loaded
for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS control bit in the PWMCON2 SFR. The UDIS
bit affects all duty cycle buffer registers and the PWM
time base period buffer, PTPER. No duty cycle
changes or period value changes will have effect while
UDIS = 1.
Note:
The FLTA pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON register are cleared, then
the FLTA pin could be used as a general
purpose interrupt pin. The FLTA pin has
an interrupt vector, interrupt flag bit and
interrupt priority bits associated with it.
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