- 您现在的位置：买卖IC网 > PDF目录80519 > MB95F478HPMC2-G-SNE2 (FUJITSU LTD) MICROCONTROLLER, PQFP64 PDF资料下载
参数资料
| 型号： | MB95F478HPMC2-G-SNE2 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PQFP64 |
| 封装： | 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 50/76页 |
| 文件大小： | 3707K |
| 代理商： | MB95F478HPMC2-G-SNE2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
MB95410H/470H Series
54
DS702-00004-0v01-E
(2) Source Clock/Machine Clock
(VCC = 5.0 V
± 10%, VSS = 0.0 V, TA = 40° C to +85° C)
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the division
ratio set by the machine clock divide ratio select bits (SYCC:DIV1, DIV0). In addition, a source clock can be
selected from the following.
Main clock divided by 2
PLL multiplication of main clock (select from 2, 2.5, 4 multiplication)
Main CR clock divided by 2
Subclock divided by 2
Sub-CR clock divided by 2
(Continued)
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
tSCLK
—
61.5
—
2000
ns
When the main oscillation clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
61.5
—
2000
ns
When the main oscillation clock is used
Min: FCH = 8.125 MHz, multiplied by the
PLL multiplier of 2
Max: FCH = 1 MHz, divided by 2
80
—
1000
ns
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
—61
—
s
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—20
—
s
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Source clock
frequency
FSP
—
0.50
—
16.25
MHz When the main oscillation clock is used
1
—
12.5
MHz When the main CR clock is used
FSPL
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
80
—
16000
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
s
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
s
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
Machine clock
frequency
FMP
—
0.031
—
16.25
MHz When the main oscillation clock is used
0.0625
—
12.5
MHz When the main CR clock is used
FMPL
1.024
—
16.384
kHz When the sub-oscillation clock is used
3.125
—
50
kHz
When the sub-CR clock is used
FCRL = 100 kHz
相关PDF资料 |
PDF描述 |
|---|---|
| MC9S08SG16E1MTJR | MICROCONTROLLER, PDSO16 |
| MK2745-20STR | 108 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| MK2751-01STR | 66 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| M37272EFSP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| M37902FECHP | 16-BIT, FLASH, MICROCONTROLLER, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB95F478KPMC1-ES-SNE2 | 制造商:FUJITSU 功能描述:8-bit FX series microcontroller |
| MB95F478KPMC2-G-SNE2 | 制造商:FUJITSU 功能描述:8-bit MCUs |
| MB95F563HWQN-G-JNERE1 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F564KPF-G-JNE2 | 功能描述:IC MCU 8BIT 20KB FLASH 20TSSOP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:8FX MB95560H 标准包装:60 系列:PSOC® 3 CY8C38xx 核心处理器:8051 芯体尺寸:8-位 速度:67MHz 连通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外围设备:电容感应，DMA，LCD，POR，PWM，WDT 输入/输出数:25 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 电压 - 电源 (Vcc/Vdd):1.71 V ~ 5.5 V 数据转换器:A/D 2x20b，D/A 4x8b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:48-VFQFN 裸露焊盘 包装:托盘 |
| MB95F636HP-ES-SH-SNE2 | 制造商:FUJITSU 功能描述:8-bit MCU |
发布紧急采购，3分钟左右您将得到回复。