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参数资料
| 型号： | MB95F478HPMC2-G-SNE2 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PQFP64 |
| 封装： | 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 61/76页 |
| 文件大小： | 3707K |
| 代理商： | MB95F478HPMC2-G-SNE2 |
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MB95410H/470H Series
64
DS702-00004-0v01-E
(Continued)
(VCC = 5.0 V
± 10%, AVSS = VSS = 0.0 V, TA = 40° C to +85° C)
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK
≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK
≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK
≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK
≤ 10 MHz
Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK
≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK
≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK
≤ 10 MHz
Parameter
Symbol
Pin
name
Conditions
Value*2
Unit
Remarks
Min
Max
Start condition
detection
tHD;STA
SCL,
SDA
R = 1.7 k
Ω,
C = 50 pF*1
2 tMCLK
20
—ns
Not detected when
1 tMCLK is used at
reception
Stop condition
detection
tSU;STO
SCL,
SDA
2 tMCLK
20
—ns
Not detected when
1 tMCLK is used at
reception
Restart condition
detection condition
tSU;STA
SCL,
SDA
2 tMCLK
20
—ns
Not detected when
1 tMCLK is used at
reception
Bus free time
tBUF
SCL,
SDA
2 tMCLK
20
—
ns
At reception
Data hold time
tHD;DAT
SCL,
SDA
2 tMCLK
20
—ns
At slave
transmission mode
Data setup time
tSU;DAT
SCL,
SDA
tLOW
3 tMCLK 20
—ns
At slave
transmission mode
Data hold time
tHD;DAT
SCL,
SDA
0
—
ns
At reception
Data setup time
tSU;DAT
SCL,
SDA
tMCLK
20
—
ns
At reception
SDA
↓→SCL↑
(at wakeup
function)
tWAKEUP
SCL,
SDA
Oscillation
stabilization wait
time
+2 tMCLK 20
—ns
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