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参数资料
| 型号： | MBM29DL161BE-90PBT |
| 厂商： | FUJITSU LTD |
| 元件分类： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封装： | PLASTIC, FBGA-48 |
| 文件页数： | 27/76页 |
| 文件大小： | 1145K |
| 代理商： | MBM29DL161BE-90PBT |
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MBM29DL16XTE/BE70/90
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After the Program Resume command (30 h) is written, the device reverts to programming. The bank addresses
of sector being suspended should be set when writing the Program Resume command. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program
operation.See “Write Operation Status” for more information.
The system may also write the autoselect command sequence when the device in the Program Suspend mode.
The device allows reading autoselect codes at the addresses within programming sectors, since the codes are
not stored in the memory. When the device exits the autoselect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See“Autoselect Command” for more information.
The system must write the Program Resume command (address bits are “Bank Address”) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Resume command are ignored.
Another Program Suspend command can be written after the device has resume programming.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ7 is “1” (See “Write Operation Status”.) at which time the device
returns to read the mode.
Chip Erase Time; Sector Erase Time
× All sectors + Chip Program Time (Preprogramming)
“(2) Embedded EraseTM Algorithm” in sFLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.
After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29DL16XTE/BE
Command Definitions Table” in sDEVICE BUS OPERATION. This sequence is followed with writes of the Sector
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than “tTOW” otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever
happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE,
whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine
if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than
Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the
previous command string. Resetting the devices once execution has begun will corrupt the data in the sector.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MBM29DL161BE-90TN | 制造商:SPANSION 制造商全称:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation |
| MBM29DL161BE-90TR | 制造商:SPANSION 制造商全称:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation |
| MBM29DL161TD | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M x 8/1M x 16) BIT Dual Operation |
| MBM29DL161TD-70PBT | 制造商:SPANSION 制造商全称:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation |
| MBM29DL161TD-70PFTN | 制造商:SPANSION 制造商全称:SPANSION 功能描述:FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT Dual Operation |
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