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参数资料
| 型号： | MBM29DL32TF70TN |
| 厂商： | FUJITSU LTD |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封装： | PLASTIC, TSOP1-48 |
| 文件页数： | 32/70页 |
| 文件大小： | 862K |
| 代理商： | MBM29DL32TF70TN |
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MBM29DL32TF/BF-70
38
also should note whether the value of DQ5 is high (see “15. DQ5”) . If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high.
If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-
mining the status as described in the previous paragraph. Alternatively it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to “4. Toggle Bit Algorithm” in sFLOW CHART.)
Toggle Bit Status Table
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle.
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.
20. RY/BY
Ready/Busy
The MBM29DL32TF/BF provide a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy
with either a program or erase operation. If the output is high, the devices are ready to accept any read/program
or erase operation. If the MBM29DL32TF/BF are placed in an Erase Suspend mode, the RY/BY output will be
high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “10. RY/BY Timing Diagram during Program/Erase Opera-
tions” and “11. RESET, RY/BY Timing Diagram” in sTIMING DIAGRAM for a detailed timing diagram. The RY/
BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiple of devices may
be connected to the host system via more than one RY/BY pin in parallel.
21. Data Protection
The MBM29DL32TF/BF are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the devices automatically
reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
22. Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO. If VCC
< VLKO, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level
is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Toggle *1
Erase-Suspend Read
(Erase-Suspended Sector)
11
Toggle
Erase-Suspend Program
DQ7
Toggle
1 *2
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相关代理商/技术参数 |
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| MBM29DL32XBD | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32M (4M X 8/2M X 16) BIT Dual Operation |
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