参数资料
| 型号： | MC100EP196FAR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/18页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 标准包装： | 1 |
| 系列： | 100EP |
| 标片/步级数： | 1024 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 2.36ns |
| 接头增量： | 10ps |
| 可用的总延迟： | 2.36ns ~ 12.258ns |
| 独立延迟数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 剪切带 (CT) |
| 其它名称： | MC100EP196FAROSCT |
MC100EP196
http://onsemi.com
13
Cascading Multiple EP196s
To increase the programmable range of the EP196,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range; however, this
increase is at the expense of a longer minimum delay.
Figure 6 illustrates the interconnect scheme for cascading
two EP196s. As can be seen, this scheme can easily be
expanded for larger EP196 chains. The D10 input of the
EP196 is the cascade control pin and when assert
HIGH switches output pin CASCADE to HIGH and
pin CASCADE to LOW. With the interconnect scheme of
Figure 6 when D10 is asserted, it signals the need for a larger
programmable range than is achievable with a single device.
The A11 address can be added to generate a cascade output
for the next EP196. For a 2device configuration, A11 is not
required.
Figure 6. Cascading Interconnect Architecture
VEE
D0
VCC
Q
FTUNE
VCC
CASCADE
EN
SETMAX
V
CC
V
EE
LEN
D2 D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3
D4
D5
D6
D7
D9
D10
IN
VCF
INPUT
OUTPUT
EP196
CHIP #2
EP196
CHIP #1
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Need if Chip #3 is used
DAC
VEE
D0
VCC
Q
FTUNE
VCC
CASCADE
EN
SETMAX
V
CC
V
EE
LEN
D2 D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3
D4
D5
D6
D7
D9
D10
IN
VCF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC100EP196FAR2G | 功能描述:延迟线/计时元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| MC100EP210S | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2.5V1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210S_06 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:2.5V 1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210SFA | 功能描述:时钟缓冲器 2.5V 1:5 Dual Diff RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| MC100EP210SFAG | 功能描述:时钟缓冲器 2.5V 1:5 Dual Diff LVDS Clock Driver RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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